📄 xlli_lowlev_init.s
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cmp r2, #28 @ Is L=28?
ldreq r3, =xlli_MSC0_182 @ Yes - load values
ldreq r5, =xlli_DTC_182
ldreq r7, =xlli_DRI_182
cmp r2, #29 @ Is L=29?
ldreq r3, =xlli_MSC0_188 @ Yes - load values
ldreq r5, =xlli_DTC_188
ldreq r7, =xlli_DRI_188
cmp r2, #30 @ Is L=30?
ldreq r3, =xlli_MSC0_195 @ Yes - load values
ldreq r5, =xlli_DTC_195
ldreq r7, =xlli_DRI_195
cmp r2, #31 @ Is L=31?
ldreq r3, =xlli_MSC0_201 @ Yes - load values
ldreq r5, =xlli_DTC_201
ldreq r7, =xlli_DRI_201
b XLLI_Done_MSC0_Opt_Update
xlli_A1B1_Table:
cmp r2, #2 @ Is L=2?
ldreq r3, =xlli_MSC0_26 @ Yes - load values
ldreq r5, =xlli_DTC_26
ldreq r7, =xlli_DRI_26
cmp r2, #3 @ Is L=3?
ldreq r3, =xlli_MSC0_39 @ Yes - load values
ldreq r5, =xlli_DTC_39
ldreq r7, =xlli_DRI_39
cmp r2, #4 @ Is L=4?
ldreq r3, =xlli_MSC0_52 @ Yes - load values
ldreq r5, =xlli_DTC_52
ldreq r7, =xlli_DRI_52
cmp r2, #5 @ Is L=5?
ldreq r3, =xlli_MSC0_65 @ Yes - load values
ldreq r5, =xlli_DTC_65
ldreq r7, =xlli_DRI_65
cmp r2, #6 @ Is L=6?
ldreq r3, =xlli_MSC0_78 @ Yes - load values
ldreq r5, =xlli_DTC_78
ldreq r7, =xlli_DRI_78
cmp r2, #7 @ Is L=7?
ldreq r3, =xlli_MSC0_91 @ Yes - load values
ldreq r5, =xlli_DTC_91
ldreq r7, =xlli_DRI_91
cmp r2, #8 @ Is L=8?
ldreq r3, =xlli_MSC0_104 @ Yes - load values
ldreq r5, =xlli_DTC_104
ldreq r7, =xlli_DRI_104
cmp r2, #9 @ Is L=9?
ldreq r3, =xlli_MSC0_117 @ Yes - load values
ldreq r5, =xlli_DTC_117
ldreq r7, =xlli_DRI_117
cmp r2, #10 @ Is L=10?
ldreq r3, =xlli_MSC0_130 @ Yes - load values
ldreq r5, =xlli_DTC_130
ldreq r7, =xlli_DRI_130
cmp r2, #11 @ Is L=11?
ldreq r3, =xlli_MSC0_143 @ Yes - load values
ldreq r5, =xlli_DTC_143
ldreq r7, =xlli_DRI_143
cmp r2, #12 @ Is L=12?
ldreq r3, =xlli_MSC0_156 @ Yes - load values
ldreq r5, =xlli_DTC_156
ldreq r7, =xlli_DRI_156
cmp r2, #13 @ Is L=13?
ldreq r3, =xlli_MSC0_169 @ Yes - load values
ldreq r5, =xlli_DTC_169
ldreq r7, =xlli_DRI_169
cmp r2, #14 @ Is L=14?
ldreq r3, =xlli_MSC0_182 @ Yes - load values
ldreq r5, =xlli_DTC_182
ldreq r7, =xlli_DRI_182
cmp r2, #15 @ Is L=15?
ldreq r3, =xlli_MSC0_195 @ Yes - load values
ldreq r5, =xlli_DTC_195
ldreq r7, =xlli_DRI_195
cmp r2, #16 @ Is L=16?
ldreq r3, =xlli_MSC0_208 @ Yes - load values
ldreq r5, =xlli_DTC_208
ldreq r7, =xlli_DRI_208
XLLI_Done_MSC0_Opt_Update:
@
@ Update MSC0
@
orr r4, r4, r3 @ Update the RDF, RDN and RRR bits
str r4, [r1, #xlli_MSC0_offset] @ Set the new MSC0 value
ldr r4, [r1, #xlli_MSC0_offset] @ Read MSC0 value back to lock the values
@
@ Update DRI bits
@
orr r8, r8, r7 @ Update the DRI bits
str r8, [r1, #xlli_MDREFR_offset] @ Set the new MDREFR value
@
@ Update DTC bits
@
orr r6, r6, r5 @ Update DTC0 and DTC2 bits
str r6, [r1, #xlli_MDCNFG_offset] @ Write back the MDCNFG value
mov pc, lr @ return to calling routine
ENDFUNC
.ltorg
@**************************************************************************************************
@
@ ******************************************************
@ ********** **********
@ ********** INITIALIZE (MASK) ALL INTERRUPTS **********
@ ********** **********
@ ******************************************************
@
@ NOTE: On system reset, all interrupts should be cleared by hardware.
@ This enforces disabling of all interrupts to HW boot default conditions.
@
xlli_intr_init: FUNCTION
ldr r4, =xlli_INTERREGS_PHYSICAL_BASE @ Load controller physical base address
ldr r2, =0x0 @ zero out a work register
str r2, [r4, #xlli_ICMR_offset] @ Mask all interrupts (clear mask register)
str r2, [r4, #xlli_ICMR2_offset] @ Mask all interrupts (clear mask register) 2
str r2, [r4, #xlli_ICLR_offset] @ Clear the interrupt level register
str r2, [r4, #xlli_ICLR2_offset] @ Clear the interrupt level register 2
str r2, [r4, #xlli_ICCR_offset] @ Clear Interrupt Control Register
str r2, [r4, #xlli_ICCR2_offset] @ Clear Interrupt Control Register 2
mov pc, lr @ return to calling routine
ENDFUNC
@**************************************************************************************************
@
@ **********************************************
@ ********** **********
@ ********** INITIALIZE CLOCK MANAGER **********
@ ********** **********
@ **********************************************
@
@ Disable the peripheral clocks, and set the core clock frequency
@
@ NOTE: The Change Frequency Sequence should be called after this function in order
@ for the clock frequencies set in the CCCR register to take effect.
@
@ The code then spins on the oscillator OK bit until the oscilator is stable
@ which can take as long as two seconds.
@
xlli_clks_init: FUNCTION
@ Turn Off ALL on-chip peripheral clocks for re-configuration
@
ldr r4, =xlli_CLKREGS_PHYSICAL_BASE@ Load clock registers base address
ldr r1, =0x400000 @ Forces memory clock to stay ON!!
ldr r2, =xlli_CKEN_value @ Get any other bits required from the include file
orr r1, r1, r2 @ OR everything together
str r1, [r4, #xlli_CKEN_offset] @ ... and write out to the clock enable register
@
@ Set Crystal: Memory Freq, Memory:RunMode Freq, RunMode, TurboMode Freq Multipliers,
@ set RunMode & TurboMode to default frequency.
@
ldr r2, =xlli_CCCR_value @ Get CORE_CLK_DEFAULT value
str r2, [r4, #xlli_CCCR_offset] @ Write to the clock config register
@
@ Enable the 32 KHz oscillator and set the 32KHz output enable bits
@
mov r1, #(xlli_OSCC_OON | xlli_OSCC_TOUT_EN)
str r1, [r4, #xlli_OSCC_offset] @ for RTC and Power Manager
@
@ Init Real Time Clock (RTC) registers
@
ldr r4, =xlli_RTCREGS_PHYSICAL_BASE @ Load RTC registers base address
mov r2, #0 @ Clear a work register
str r2, [r4, #xlli_RTSR_offset] @ Clear RTC Status register
str r2, [r4, #xlli_RCNR_offset] @ Clear RTC Counter Register
str r2, [r4, #xlli_RTAR_offset] @ Clear RTC Alarm Register
str r2, [r4, #xlli_SWCR_offset] @ Clear Stopwatch Counter Register
str r2, [r4, #xlli_SWAR1_offset] @ Clear Stopwatch Alarm Register 1
str r2, [r4, #xlli_SWAR2_offset] @ Clear Stopwatch Alarm Register 2
str r2, [r4, #xlli_PICR_offset] @ Clear Periodic Counter Register
str r2, [r4, #xlli_PIAR_offset] @ Clear Interrupt Alarm Register
@ mov pc, lr ; DISABLED - Return here if A0 silicon
@
@ Check the Oscillator OK (OOK) bit in clock register OSCC to insure the timekeeping oscillator
@ is enabled and stable before returning to the calling program.
@
ldr r4, =xlli_CLKREGS_PHYSICAL_BASE@ Reload clock registers base address
xlli_6:
ldr r1, [r4, #xlli_OSCC_offset] @ Get the status of the OSCC register
ands r1, r1, #xlli_OSCC_OOK @ is the oscillator OK bit set?
beq xlli_6 @ Spin in this loop until the bit is set
mov pc, lr @ return to calling routine
ENDFUNC
@**************************************************************************************************
@
@ ****************************************************************
@ ********** **********
@ ********** INITIALIZE CLOCK MANAGER (FROM SLEEP MODE) **********
@ ********** **********
@ ****************************************************************
@
@ Disable the peripheral clocks, and set the core clock frequency
@
@ The code then spins on the oscillator OK bit until the oscilator is stable
@ which can take as long as two seconds.
@
xlli_clks_init_sleepReset: FUNCTION
@ Turn Off ALL on-chip peripheral clocks for re-configuration
@
ldr r4, =xlli_CLKREGS_PHYSICAL_BASE@ Load clock registers base address
ldr r1, =0x400000 @ Forces memory clock to stay ON!!
ldr r2, =xlli_CKEN_value @ Get any other bits required from the include file
orr r1, r1, r2 @ OR everything together
str r1, [r4, #xlli_CKEN_offset] @ ... and write out to the clock enable register
@
@ Set Crystal: Memory Freq, Memory:RunMode Freq, RunMode, TurboMode Freq Multipliers,
@ set RunMode & TurboMode to default frequency.
@
ldr r2, =xlli_CCCR_value @ Get CORE_CLK_DEFAULT value
str r2, [r4, #xlli_CCCR_offset] @ Write to the clock config register
mov pc, lr @ return to calling routine
ENDFUNC
@**************************************************************************************************
@
@ ***********************************************
@ ********** **********
@ ********** FREQUENCY CHANGE SEQUENCE **********
@ ********** **********
@ ***********************************************
@
@ This subroutine initiates the frequency change sequence and restarts the memory controller
@
xlli_freq_change: FUNCTION
mrc p14, 0, r2, c6, c0, 0 @ Get present status (preserve Turbo and Fast Bus bits)
orr r2, r2, #2 @ Set the F bit
mcr p14, 0, r2, c6, c0, 0 @ initiate the frequency change sequence - Wheeeeeeeee!
@
@ If the clock frequency is chaged, the MDREFR Register must be rewritten, even
@ if it's the same value. This will result in a refresh being performed and the
@ refresh counter being reset to the reset interval. (Section 13.10.3, pg 13-17 of EAS)
@
ldr r4, =xlli_MEMORY_CONFIG_BASE @ Get memory controller base address
ldr r1, [r4, #xlli_MDREFR_offset] @ Get the current state of MDREFR
str r1, [r4, #xlli_MDREFR_offset] @ Re-write this value
mov pc, lr @ return to calling routine
ENDFUNC
@**************************************************************************************************
@
@ ********************************************************
@ ********** ⌨️ 快捷键说明
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