xllp_usim_registers.h

PXA270硬件测试源代码

/******************************************************************************
**
**  COPYRIGHT (C) 2001, 2002 Intel Corporation.
**
**  This software as well as the software described in it is furnished under
**  license and may only be used or copied in accordance with the terms of the
**  license. The information in this file is furnished for informational use
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**  a commitment by Intel Corporation. Intel Corporation assumes no
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**  in this document or any software that may be provided in association with
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:       xllp_usim_registers.h
**
**  PURPOSE: contains all USIM registers and USIM register locations
**                  
**
******************************************************************************/

#ifndef __USIM_REGISTERS_H__
#define __USIM_REGISTERS_H__

#include "xllp_defs.h"

/**
  USIM Register Definitions According to the EAS Revision 2.0
**/
typedef struct UsimRegsS
{
    XLLP_VUINT32_T RBR;		/* Receive Buffer (Read Only) */
    XLLP_VUINT32_T THR;		/* Transmit Buffer (Write Only) */
    XLLP_UINT32_T IER;		/* Interrupt Enable (R/W) */
    XLLP_UINT32_T IIR;		/* Interrupt I.D.(Read Only) */
    XLLP_UINT32_T FCR;		/* FIFO Control Register (Write Only) */
    XLLP_VUINT32_T FSR;		/* FIFO Status Register (Read Only) */
    XLLP_UINT32_T ECR;		/* Error Control Register (R/W) */
    XLLP_UINT32_T LCR;		/* Line Control Register(R/W) */
    XLLP_UINT32_T CCR;		/* Card Control Register(R/W) */
    XLLP_VUINT32_T LSR;		/* Line Status Register(Read Only) */
    XLLP_UINT32_T EGTR;		/* Extra Guard Time Register */
    XLLP_UINT32_T BGTR;		/* Block Guard Time Register */
    XLLP_UINT32_T TOR;		/* Time Out Register */
    XLLP_UINT32_T CLKR;		/* Clock Register */
    XLLP_UINT32_T DLR;		/* Divisor Latch Register (Byte, R/W) */
    XLLP_UINT32_T FLR;		/* Elapsed Time Out Register */
    XLLP_UINT32_T CWTR;		/* Character Wait Register */
	XLLP_UINT32_T BWTR;		/* Block Wait Register */
} XLLP_USIM_T;

/**
 USIM Register Fields According to the EAS Revision 2.0 
**/

/* Receive Buffer Register (RBR) */
#define XLLP_USIM_RBR_PERR	0x100		/* Parity Error */
#define XLLP_USIM_RBR_RB	0xFF		/* Receive Byte */
#define XLLP_USIM_RBR_VALID	0x1FF		/* Received byte + parity error */

/* Transmit Holding Register (THR) */
#define XLLP_USIM_THR_TB	0xFF		/* Transmit Byte */

/* Interrupt Enables Register (IER) */
#define XLLP_USIM_IER_DMA_TX		0x8000	/* Enable Transmit Requests */
#define XLLP_USIM_IER_DMA_RX		0x4000	/* Enable Receive Requests */
#define XLLP_USIM_IER_DMA_TIME		0x2000	/* Enable DMA request in case of a time out */
#define XLLP_USIM_IER_CARD_DET		0x1000	/* Enable Card Detection */
#define XLLP_USIM_IER_TDR			0x200	/* Enable Transmitter Data Refill Interrupt*/
#define XLLP_USIM_IER_RDR			0x100	/* Enable Receiver Data Ready Interrupt*/
#define XLLP_USIM_IER_BWT			0x40	/* Enable Block Waiting Time Interrupt */
#define XLLP_USIM_IER_CWT			0x20	/* Enable Character Waiting Time Interrupt*/
#define XLLP_USIM_IER_TIME			0x10	/* Enable Receiver Time Out Interrupt*/
#define XLLP_USIM_IER_FRAMERR		0x8		/* Enable Framing Error Interrupt*/
#define XLLP_USIM_IER_T0ERR			0x4		/* Enable T=0 Error Interrupt*/
#define XLLP_USIM_IER_PERR			0x2		/* Enable Parity Error Interrupt*/
#define XLLP_USIM_IER_OVRN			0x1		/* Enable Receiver Data Overrun Interrupt*/
#define XLLP_USIM_IER_VALID_MASK	0xFB7F	/* Enable Receiver Data Overrun Interrupt*/

/* Interrupt Identification Register (IIR) */
#define XLLP_USIM_IIR_CARD_DET			0x1000	/* Card Detection */
#define XLLP_USIM_IIR_TDR				0x200	/* Transmitter Data Refill Interrupt is Pending */
#define XLLP_USIM_IIR_RDR				0x100	/* Receiver Data Refill Interrupt is Pending */
#define XLLP_USIM_IIR_BWT				0x40	/* Block Waiting Time Interrupt is Pending*/
#define XLLP_USIM_IIR_CWT				0x20	/* Chracter Waiting Time interrupt is Pending */
#define XLLP_USIM_IIR_TIME				0x10	/* Receiver Time Out Interrupt is Pending */
#define XLLP_USIM_IIR_FRAMERR			0x8		/* Framing Error Interrupt is Pending */		
#define XLLP_USIM_IIR_T0ERR				0x4		/* T=0 Error Interrupt is Pending */
#define XLLP_USIM_IIR_PERR				0x2		/* Parity Error Interrupt is Pending */
#define XLLP_USIM_IIR_OVRNERR			0x1		/* Receiver Data Overrun Interrupt is Pending */
#define XLLP_USIM_IIR_VALID_MASK	0x137F	/* Valid Interrupt Sources Mask */

/* FIFO Control Register (FCR) */
#define XLLP_USIM_FCR_TX_TL		0x100	/* Transmitter Triggger Level */
#define XLLP_USIM_FCR_RX_TL		0xC0	/* Receiver Triggger Level */
#define XLLP_USIM_FCR_PEM		0x8		/* Parity Error Mask */
#define XLLP_USIM_FCR_TX_HOLD	0x4		/* Holds Transmission */
#define XLLP_USIM_FCR_RESETTF	0x2		/* Reset Transmitter FIFO */
#define XLLP_USIM_FCR_RESETRF	0x1		/* Reset Receiver FIFO */

/* FIFO Status Register (FSR) */
#define XLLP_USIM_FSR_PERR_NUM			0x7C00	/* Number of Bytes with Parity Errors in Rx FIFO */
#define XLLP_USIM_FSR_PERR_NUM_SHIFT	10		/* Field starts at bit 10 */
#define XLLP_USIM_FSR_TX_LENGTH			0x3E0	/* Remaining Bytes in the Transmit FIFO */
#define XLLP_USIM_FSR_TX_LENGTH_SHIFT	5		/* Field starts at bit 5 */
#define XLLP_USIM_FSR_RX_LENGTH			0x1F	/* Remaining Bytes in the Receive FIFO */
#define XLLP_USIM_FSR_RX_LENGTH_SHIFT	0		/* Field starts at bit 0 */
	

/* Error Control Register (ECR) */
#define XLLP_USIM_ECR_T0_REPEAT			0x80	/* Repeat character transmission */
#define XLLP_USIM_ECR_T0_CLR			0x40	/* Clear T=0 Error */
#define XLLP_USIM_ECR_PE_TL				0x18	/* Parity Error Trigger Level */
#define XLLP_USIM_ECR_PE_TL_SHIFT		3		/* Field starts at bit 3 */
#define XLLP_USIM_ECR_T0ERR_TL			0x3		/* T=0 Error Trigger Level */
#define XLLP_USIM_ECR_T0ERR_TL_SHIFT	0		/* Field starts at bit 0 */

/* Line Control Register (LCR) */
#define XLLP_USIM_LCR_TX_T1_MODE	0x10	/* Choose Transmitter Protocol */
#define XLLP_USIM_LCR_RX_T1_MODE	0x8		/* Choose Receiver Protocol */
#define XLLP_USIM_LCR_EPS			0x4		/* Even Parity Select */
#define XLLP_USIM_LCR_EPS_SHIFT		2		/* Field starts at bit 2 */
#define XLLP_USIM_LCR_ORDER			0x2		/* Transmit/Receive Bit Order */
#define XLLP_USIM_LCR_INVERSE		0x1		/* Bit Inversion */

/* Card Control Register (CCR) */
#define XLLP_USIM_CCR_TXD_FORCE		0x10	/* TXD is forced to Vlow */
#define XLLP_USIM_CCR_VCC			0x6		/* Card Voltage */
#define XLLP_USIM_CCR_VCC_SHIFT		1		/* Field starts at bit 1 */
#define XLLP_USIM_CCR_RST_CARD_N	0x1		/* Card Reset on 0 */

/* Line Status Register (LSR) */
#define XLLP_USIM_LSR_RXD			0x8000	/* Reflects sampled data on I/O line */
#define XLLP_USIM_LSR_RX_WORKING	0x4000	/* Receiver is in process */
#define XLLP_USIM_LSR_TX_WORKING	0x2000	/* Transmitter is in Process */
#define XLLP_USIM_LSR_RX_EMPTY_N	0x1000	/* Receiver FIFO is not Empty */
#define XLLP_USIM_LSR_TX_REFILL		0x800	/* # of Chars in Tx FIFO is less than Triggrt Level */
#define XLLP_USIM_LSR_TX_BWT		0x40	/* Block Waiting Time is Over */
#define XLLP_USIM_LSR_TX_CWT		0x20	/* Character Waiting Time is Over */
#define XLLP_USIM_LSR_TIMEO			0x10	/* Time Out Detected while receiving a Char. clears when reading RBR */
#define XLLP_USIM_LSR_FRMERR		0x8		/* Framing Error has occurred */
#define XLLP_USIM_LSR_T0ERR			0x4		/* T=0 Errors > Trigger Level */
#define XLLP_USIM_LSR_PERR			0x2		/* Parity Errors > Trigger Level */
#define XLLP_USIM_LSR_OVRNE			0x1		/* Overrun Errors */
#define XLLP_USIM_LSR_VALID_MASK	0x1		/* Overrun Errors */


/* Extra Guard Time Register (EGTR) */
#define XLLP_USIM_EGTR_EGTM 0xFF			/* Extra Guard Time Moments */


/* Block Guard Time Register (BGTR) */
#define XLLP_USIM_BGTR_BGT 0xFF				/* Block Guard Time */

/* Time Out Register (TOR) */
#define XLLP_USIM_TOR_TO 0xFF				/* Time Out: Number of total Time Out moments */


/* Clock Register (CLKR) */
#define XLLP_USIM_CLKR_STOP_CLK_USIM 0x8000	/* Start/Stop USIM clock control */
#define XLLP_USIM_CLKR_STOP_LEVEL	 0x4000	/* Determines Clock Stop Level */
#define XLLP_USIM_CLKR_STOP_UCLK	 0x2000	/* Enables Clock Stop */
#define XLLP_USIM_CLKR_RQST			 0x1000	/* Clock Change Request */
#define XLLP_USIM_CLKR_DIVISOR		 0xFF	/* Card Freq = 48Mhz/ (2 * DIVISOR) */

/* Divisor Latch Register (DLR) */
#define XLLP_USIM_DLR_DIVISOR		0xFFFF	/* Number of Samples/bit = FACTOR + 1 */

/* Factor Latch Register (FLR) */
#define XLLP_USIM_FLR_FACTOR		0xFF	/* Determine the number of samples per bit.*/

/* Character Width Time Register (CWTR) */
#define XLLP_USIM_CWTR_CWT	0xFFFF			/* Character Waiting time in moments */

/* Block Waiting Time Register (BWTR) */
#define XLLP_USIM_BWTR_BWT			0xFFFF	/* Block Waiting time in moments*/


/* USIM defines for Pwr Manager Regs */
//added in support of USIM as indicated by spec.
/* Pwr Mgr USIM Card Control/Status Register (PUCR) */
#define XLLP_USIM_PUCR_ENUDET_SHIFT		0
#define XLLP_USIM_PUCR_USIM114_SHIFT	2  
#define XLLP_USIM_PUCR_USIM115_SHIFT	3
#define XLLP_USIM_PUCR_UDETS_SHIFT		5

#define XLLP_USIM_PUCR_UDETS_SET		0x1 << XLLP_USIM_PUCR_UDETS_SHIFT

#endif //__USIM_REGISTERS_H__