xllp_udc.h

PXA270硬件测试源代码

/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:  		xllp_udc.h
**
**  PURPOSE:   		This files contains the definitions for UDC 
**					(USB Device controller)
**
**  LAST MODIFIED:  1/25/2001
**
******************************************************************************/

#ifndef _xllp_udc_h
#define _xllp_udc_h

/*
************************************************************************************
*							CONSTANTS 
************************************************************************************
*/

// Masks for UDC Registers

// UDC Control Register (UDCCR)
#define XLLP_UDC_UDCCR_UDE          ( 0x1U << 0 )	// UDC enabled
#define XLLP_UDC_UDCCR_UDA			( 0x1U << 1 )	// READ-ONLY: udc is active
#define XLLP_UDC_UDCCR_UDR			( 0x1U << 2 )	// Forces the usb out of suspend state
#define XLLP_UDC_UDCCR_EMCE			( 0x1U << 3 )	// The Endpoint memory config. has an error
#define XLLP_UDC_UDCCR_SMAC			( 0x1U << 4 )	// Switch Endpoint memory to Active config.
                                                    // Active interface and Alternate Interface
#define XLLP_UDC_UDCCR_AAISN_SHIFT  5               // Shift and a mask for the Alternate Interface 
#define XLLP_UDC_UDCCR_AAISN_MASK   ( 0x7U << XLLP_UDC_UDCCR_AAISN_SHIFT )  // Settings  (0-7)
#define XLLP_UDC_UDCCR_AIN_SHIFT    8               // Shift and a mask for the Interface
#define XLLP_UDC_UDCCR_AIN_MASK     ( 0x7U << XLLP_UDC_UDCCR_AIN_SHIFT )    // Number    (0-7)
#define XLLP_UDC_UDCCR_ACN_SHIFT    11              // Shift and a mask for the Configuration
#define XLLP_UDC_UDCCR_ACN_MASK     ( 0x3U << XLLP_UDC_UDCCR_ACN_SHIFT )    // Number    (0-3)
#define XLLP_UDC_UDCCR_DRWF			( 0x1U << 16 )	// Device Remote Wakeup Feature

// UDC Interrupt Control Register 0 (UDCICR0)
#define XLLP_UDC_UDCICR0_IE0_0		( 0x1U << 0 )	// Packet Complete Interrupt Enable - Endpoint 0
#define XLLP_UDC_UDCICR0_IE0_1		( 0x1U << 1 )   // FIFO Error Interrupt Enable - Endpoint 0
#define XLLP_UDC_UDCICR0_IEA_0		( 0x1U << 2 )	// Packet Complete Interrupt Enable - Endpoint A
#define XLLP_UDC_UDCICR0_IEA_1		( 0x1U << 3 )   // FIFO Error Interrupt Enable - Endpoint A
#define XLLP_UDC_UDCICR0_IEB_0		( 0x1U << 4 )	// Packet Complete Interrupt Enable - Endpoint B
#define XLLP_UDC_UDCICR0_IEB_1		( 0x1U << 5 )   // FIFO Error Interrupt Enable - Endpoint B
#define XLLP_UDC_UDCICR0_IEC_0		( 0x1U << 6 )	// Packet Complete Interrupt Enable - Endpoint C
#define XLLP_UDC_UDCICR0_IEC_1		( 0x1U << 7 )   // FIFO Error Interrupt Enable - Endpoint C
#define XLLP_UDC_UDCICR0_IED_0		( 0x1U << 8 )	// Packet Complete Interrupt Enable - Endpoint D
#define XLLP_UDC_UDCICR0_IED_1		( 0x1U << 9 )   // FIFO Error Interrupt Enable - Endpoint D
#define XLLP_UDC_UDCICR0_IEE_0		( 0x1U << 10 )	// Packet Complete Interrupt Enable - Endpoint E
#define XLLP_UDC_UDCICR0_IEE_1		( 0x1U << 11 )  // FIFO Error Interrupt Enable - Endpoint E
#define XLLP_UDC_UDCICR0_IEF_0		( 0x1U << 12 )	// Packet Complete Interrupt Enable - Endpoint F
#define XLLP_UDC_UDCICR0_IEF_1		( 0x1U << 13 )  // FIFO Error Interrupt Enable - Endpoint F
#define XLLP_UDC_UDCICR0_IEG_0		( 0x1U << 14 )	// Packet Complete Interrupt Enable - Endpoint G
#define XLLP_UDC_UDCICR0_IEG_1		( 0x1U << 15 )  // FIFO Error Interrupt Enable - Endpoint G
#define XLLP_UDC_UDCICR0_IEH_0		( 0x1U << 16 )	// Packet Complete Interrupt Enable - Endpoint H
#define XLLP_UDC_UDCICR0_IEH_1		( 0x1U << 17 )  // FIFO Error Interrupt Enable - Endpoint H
#define XLLP_UDC_UDCICR0_IEI_0		( 0x1U << 18 )	// Packet Complete Interrupt Enable - Endpoint I
#define XLLP_UDC_UDCICR0_IEI_1		( 0x1U << 19 )  // FIFO Error Interrupt Enable - Endpoint I
#define XLLP_UDC_UDCICR0_IEJ_0		( 0x1U << 20 )	// Packet Complete Interrupt Enable - Endpoint J
#define XLLP_UDC_UDCICR0_IEJ_1		( 0x1U << 21 )  // FIFO Error Interrupt Enable - Endpoint J
#define XLLP_UDC_UDCICR0_IEK_0		( 0x1U << 22 )	// Packet Complete Interrupt Enable - Endpoint K
#define XLLP_UDC_UDCICR0_IEK_1		( 0x1U << 23 )  // FIFO Error Interrupt Enable - Endpoint K
#define XLLP_UDC_UDCICR0_IEL_0		( 0x1U << 24 )	// Packet Complete Interrupt Enable - Endpoint L
#define XLLP_UDC_UDCICR0_IEL_1		( 0x1U << 25 )  // FIFO Error Interrupt Enable - Endpoint L
#define XLLP_UDC_UDCICR0_IEM_0		( 0x1U << 26 )	// Packet Complete Interrupt Enable - Endpoint M
#define XLLP_UDC_UDCICR0_IEM_1		( 0x1U << 27 )  // FIFO Error Interrupt Enable - Endpoint M
#define XLLP_UDC_UDCICR0_IEN_0		( 0x1U << 28 )	// Packet Complete Interrupt Enable - Endpoint N
#define XLLP_UDC_UDCICR0_IEN_1		( 0x1U << 29 )  // FIFO Error Interrupt Enable - Endpoint N
#define XLLP_UDC_UDCICR0_IEP_0		( 0x1U << 30 )	// Packet Complete Interrupt Enable - Endpoint P
#define XLLP_UDC_UDCICR0_IEP_1		( 0x1U << 31 )  // FIFO Error Interrupt Enable - Endpoint P

#define XLLP_UDC_UDCICR0_ENABLE_ALL 0xFFFFFFFE      // Mask to enable all endpoint A - P interrupts

// UDC Interrupt Control Register 1 (UDCICR1)
#define XLLP_UDC_UDCICR1_IEQ_0		( 0x1U << 0 )	// Packet Complete Interrupt Enable - Endpoint Q
#define XLLP_UDC_UDCICR1_IEQ_1		( 0x1U << 1 )   // FIFO Error Interrupt Enable - Endpoint Q
#define XLLP_UDC_UDCICR1_IER_0		( 0x1U << 2 )	// Packet Complete Interrupt Enable - Endpoint R
#define XLLP_UDC_UDCICR1_IER_1		( 0x1U << 3 )   // FIFO Error Interrupt Enable - Endpoint R
#define XLLP_UDC_UDCICR1_IES_0		( 0x1U << 4 )	// Packet Complete Interrupt Enable - Endpoint S
#define XLLP_UDC_UDCICR1_IES_1		( 0x1U << 5 )   // FIFO Error Interrupt Enable - Endpoint S
#define XLLP_UDC_UDCICR1_IET_0		( 0x1U << 6 )	// Packet Complete Interrupt Enable - Endpoint T
#define XLLP_UDC_UDCICR1_IET_1		( 0x1U << 7 )   // FIFO Error Interrupt Enable - Endpoint T
#define XLLP_UDC_UDCICR1_IEU_0		( 0x1U << 8 )	// Packet Complete Interrupt Enable - Endpoint U
#define XLLP_UDC_UDCICR1_IEU_1		( 0x1U << 9 )   // FIFO Error Interrupt Enable - Endpoint U
#define XLLP_UDC_UDCICR1_IEV_0		( 0x1U << 10 )	// Packet Complete Interrupt Enable - Endpoint V
#define XLLP_UDC_UDCICR1_IEV_1		( 0x1U << 11 )  // FIFO Error Interrupt Enable - Endpoint V
#define XLLP_UDC_UDCICR1_IEW_0		( 0x1U << 12 )	// Packet Complete Interrupt Enable - Endpoint W
#define XLLP_UDC_UDCICR1_IEW_1		( 0x1U << 13 )  // FIFO Error Interrupt Enable - Endpoint W
#define XLLP_UDC_UDCICR1_IEX_0		( 0x1U << 14 )	// Packet Complete Interrupt Enable - Endpoint X
#define XLLP_UDC_UDCICR1_IEX_1		( 0x1U << 15 )  // FIFO Error Interrupt Enable - Endpoint X
#define XLLP_UDC_UDCICR1_IERS		( 0x1U << 27 )  // Interrupt Enable - Reset
#define XLLP_UDC_UDCICR1_IESU		( 0x1U << 28 )  // Interrupt Enable - Suspend
#define XLLP_UDC_UDCICR1_IERU		( 0x1U << 29 )  // Interrupt Enable - Resume
#define XLLP_UDC_UDCICR1_IESOF		( 0x1U << 30 )  // Interrupt Enable - SOF
#define XLLP_UDC_UDCICR1_IECC		( 0x1U << 31 )  // Interrupt Enable - Configuration Change

#define XLLP_UDC_UDCICR1_EVENTS     ( 0x1FU << 27 ) // Mask to enable all event interrupts
#define XLLP_UDC_UDCICR1_ENABLE_ALL 0xFFFF          // Mask to enable all endpoint Q - X interrupts

// UDC Interrupt Status Register 0 (UDCICR0)
#define XLLP_UDC_UDCISR0_IR0_0		( 0x1U << 0 )	// Packet Complete Interrupt Request - Endpoint 0
#define XLLP_UDC_UDCISR0_IR0_1		( 0x1U << 1 )   // FIFO Error Interrupt Request - Endpoint 0
#define XLLP_UDC_UDCISR0_IRA_0		( 0x1U << 2 )	// Packet Complete Interrupt Request - Endpoint A
#define XLLP_UDC_UDCISR0_IRA_1		( 0x1U << 3 )   // FIFO Error Interrupt Request - Endpoint A
#define XLLP_UDC_UDCISR0_IRB_0		( 0x1U << 4 )	// Packet Complete Interrupt Request - Endpoint B
#define XLLP_UDC_UDCISR0_IRB_1		( 0x1U << 5 )   // FIFO Error Interrupt Request - Endpoint B
#define XLLP_UDC_UDCISR0_IRC_0		( 0x1U << 6 )	// Packet Complete Interrupt Request - Endpoint C
#define XLLP_UDC_UDCISR0_IRC_1		( 0x1U << 7 )   // FIFO Error Interrupt Request - Endpoint C
#define XLLP_UDC_UDCISR0_IRD_0		( 0x1U << 8 )	// Packet Complete Interrupt Request - Endpoint D
#define XLLP_UDC_UDCISR0_IRD_1		( 0x1U << 9 )   // FIFO Error Interrupt Request - Endpoint D
#define XLLP_UDC_UDCISR0_IRE_0		( 0x1U << 10 )	// Packet Complete Interrupt Request - Endpoint E
#define XLLP_UDC_UDCISR0_IRE_1		( 0x1U << 11 )  // FIFO Error Interrupt Request - Endpoint E
#define XLLP_UDC_UDCISR0_IRF_0		( 0x1U << 12 )	// Packet Complete Interrupt Request - Endpoint F
#define XLLP_UDC_UDCISR0_IRF_1		( 0x1U << 13 )  // FIFO Error Interrupt Request - Endpoint F
#define XLLP_UDC_UDCISR0_IRG_0		( 0x1U << 14 )	// Packet Complete Interrupt Request - Endpoint G
#define XLLP_UDC_UDCISR0_IRG_1		( 0x1U << 15 )  // FIFO Error Interrupt Request - Endpoint G
#define XLLP_UDC_UDCISR0_IRH_0		( 0x1U << 16 )	// Packet Complete Interrupt Request - Endpoint H
#define XLLP_UDC_UDCISR0_IRH_1		( 0x1U << 17 )  // FIFO Error Interrupt Request - Endpoint H
#define XLLP_UDC_UDCISR0_IRI_0		( 0x1U << 18 )	// Packet Complete Interrupt Request - Endpoint I
#define XLLP_UDC_UDCISR0_IRI_1		( 0x1U << 19 )  // FIFO Error Interrupt Request - Endpoint I
#define XLLP_UDC_UDCISR0_IRJ_0		( 0x1U << 20 )	// Packet Complete Interrupt Request - Endpoint J
#define XLLP_UDC_UDCISR0_IRJ_1		( 0x1U << 21 )  // FIFO Error Interrupt Request - Endpoint J
#define XLLP_UDC_UDCISR0_IRK_0		( 0x1U << 22 )	// Packet Complete Interrupt Request - Endpoint K
#define XLLP_UDC_UDCISR0_IRK_1		( 0x1U << 23 )  // FIFO Error Interrupt Request - Endpoint K
#define XLLP_UDC_UDCISR0_IRL_0		( 0x1U << 24 )	// Packet Complete Interrupt Request - Endpoint L
#define XLLP_UDC_UDCISR0_IRL_1		( 0x1U << 25 )  // FIFO Error Interrupt Request - Endpoint L
#define XLLP_UDC_UDCISR0_IRM_0		( 0x1U << 26 )	// Packet Complete Interrupt Request - Endpoint M
#define XLLP_UDC_UDCISR0_IRM_1		( 0x1U << 27 )  // FIFO Error Interrupt Request - Endpoint M
#define XLLP_UDC_UDCISR0_IRN_0		( 0x1U << 28 )	// Packet Complete Interrupt Request - Endpoint N
#define XLLP_UDC_UDCISR0_IRN_1		( 0x1U << 29 )  // FIFO Error Interrupt Request - Endpoint N
#define XLLP_UDC_UDCISR0_IRP_0		( 0x1U << 30 )	// Packet Complete Interrupt Request - Endpoint P
#define XLLP_UDC_UDCISR0_IRP_1		( 0x1U << 31 )  // FIFO Error Interrupt Request - Endpoint P

// UDC Interrupt Status Register 1 (UDCICR1)
#define XLLP_UDC_UDCISR1_IRQ_0		( 0x1U << 0 )	// Packet Complete Interrupt Request - Endpoint Q
#define XLLP_UDC_UDCISR1_IRQ_1		( 0x1U << 1 )   // FIFO Error Interrupt Request - Endpoint Q
#define XLLP_UDC_UDCISR1_IRR_0		( 0x1U << 2 )	// Packet Complete Interrupt Request - Endpoint R
#define XLLP_UDC_UDCISR1_IRR_1		( 0x1U << 3 )   // FIFO Error Interrupt Request - Endpoint R
#define XLLP_UDC_UDCISR1_IRS_0		( 0x1U << 4 )	// Packet Complete Interrupt Request - Endpoint S
#define XLLP_UDC_UDCISR1_IRS_1		( 0x1U << 5 )   // FIFO Error Interrupt Request - Endpoint S
#define XLLP_UDC_UDCISR1_IRT_0		( 0x1U << 6 )	// Packet Complete Interrupt Request - Endpoint T
#define XLLP_UDC_UDCISR1_IRT_1		( 0x1U << 7 )   // FIFO Error Interrupt Request - Endpoint T
#define XLLP_UDC_UDCISR1_IRU_0		( 0x1U << 8 )	// Packet Complete Interrupt Request - Endpoint U
#define XLLP_UDC_UDCISR1_IRU_1		( 0x1U << 9 )   // FIFO Error Interrupt Request - Endpoint U
#define XLLP_UDC_UDCISR1_IRV_0		( 0x1U << 10 )	// Packet Complete Interrupt Request - Endpoint V
#define XLLP_UDC_UDCISR1_IRV_1		( 0x1U << 11 )  // FIFO Error Interrupt Request - Endpoint V
#define XLLP_UDC_UDCISR1_IRW_0		( 0x1U << 12 )	// Packet Complete Interrupt Request - Endpoint W
#define XLLP_UDC_UDCISR1_IRW_1		( 0x1U << 13 )  // FIFO Error Interrupt Request - Endpoint W
#define XLLP_UDC_UDCISR1_IRX_0		( 0x1U << 14 )	// Packet Complete Interrupt Request - Endpoint X
#define XLLP_UDC_UDCISR1_IRX_1		( 0x1U << 15 )  // FIFO Error Interrupt Request - Endpoint X
#define XLLP_UDC_UDCISR1_IRRS		( 0x1U << 27 )  // Interrupt Request - Reset
#define XLLP_UDC_UDCISR1_IRSU		( 0x1U << 28 )  // Interrupt Request - Suspend
#define XLLP_UDC_UDCISR1_IRRU		( 0x1U << 29 )  // Interrupt Request - Resume
#define XLLP_UDC_UDCISR1_IRSOF		( 0x1U << 30 )  // Interrupt Request - SOF
#define XLLP_UDC_UDCISR1_IRCC		( 0x1U << 31 )  // Interrupt Request - Configuration Change

#define XLLP_UDC_UDCISR1_EVENTS     ( 0x1FU << 27 ) // Mask to clear all event interrupts

// UDC Endpoint 0 Control/Status Register (UDCCSR0)
#define XLLP_UDC_UDCCSR0_OPC		( 0x1U << 0 )	// OUT packet to endpoint zero received
#define XLLP_UDC_UDCCSR0_IPR		( 0x1U << 1 )	// Packet has been written to endpoint zero FIFO
#define XLLP_UDC_UDCCSR0_FTF		( 0x1U << 2 )	// Flush the Tx FIFO
#define XLLP_UDC_UDCCSR0_SST		( 0x1U << 4 )	// UDC sent stall handshake
#define XLLP_UDC_UDCCSR0_FST		( 0x1U << 5 )	// Force the UDC to issue a stall handshake
#define XLLP_UDC_UDCCSR0_RNE		( 0x1U << 6 )	// There is unread data in the Rx FIFO
#define XLLP_UDC_UDCCSR0_SA			( 0x1U << 7 )	// Current packet in FIFO is part of UDC setup command

// UDC Endpoint Control/Status Registers A-X 
#define XLLP_UDC_UDCCSR_FS			( 0x1U << 0 )	// FIFO needs service
#define XLLP_UDC_UDCCSR_PC			( 0x1U << 1 )	// Packet Complete
#define XLLP_UDC_UDCCSR_EFE			( 0x1U << 2 )	// Endpoint FIFO error
#define XLLP_UDC_UDCCSR_DME			( 0x1U << 3 )	// DMA Enable
#define XLLP_UDC_UDCCSR_SST			( 0x1U << 4 )	// Sent STALL
#define XLLP_UDC_UDCCSR_FST			( 0x1U << 5 )	// Force STALL
#define XLLP_UDC_UDCCSR_BNE		    ( 0x1U << 6 )	// Buffer not empty/full
#define XLLP_UDC_UDCCSR_SP			( 0x1U << 7 )	// Short Packet
#define XLLP_UDC_UDCCSR_FEF			( 0x1U << 8 )	// Flash Endpoint FIFO
#define XLLP_UDC_UDCCSR_DPE			( 0x1U << 9 )	// Data Packet Error

// UDC Endpoint A-X Configuration Registers
#define XLLP_UDC_UDCCRZ_EE			( 0x1U << 0 )	// Endpoint Enable
#define XLLP_UDC_UDCCRZ_DE_SHIFT    1
#define XLLP_UDC_UDCCRZ_DE			( 0x1U << 1 )	// Double-buffering Enable
#define XLLP_UDC_UDCCRZ_MPS_SHIFT	2	
#define XLLP_UDC_UDCCRZ_MPS_MASK    ( 0x3FFU << XLLP_UDC_UDCCRZ_MPS_SHIFT) // Maximum Packet Size
#define XLLP_UDC_UDCCRZ_ED_SHIFT    12
#define XLLP_UDC_UDCCRZ_ED			( 0x1U << 12 )	// Endpoint Direction
#define XLLP_UDC_UDCCRZ_ET_SHIFT    13
#define XLLP_UDC_UDCCRZ_ET_MASK     ( 0x3U << XLLP_UDC_UDCCRZ_ET_SHIFT)  // Endoint Type
#define XLLP_UDC_UDCCRZ_EN_SHIFT    15
#define XLLP_UDC_UDCCRZ_EN_MASK     ( 0xFU << XLLP_UDC_UDCCRZ_EN_SHIFT)  // Endoint Number
#define XLLP_UDC_UDCCRZ_AISN_SHIFT  19
#define XLLP_UDC_UDCCRZ_AISN_MASK   ( 0x7U << XLLP_UDC_UDCCRZ_AISN_SHIFT)  // Interface Alternate Settings Number
#define XLLP_UDC_UDCCRZ_IN_SHIFT    22
#define XLLP_UDC_UDCCRZ_IN_MASK     ( 0x7U << XLLP_UDC_UDCCRZ_IN_SHIFT)    // Interface Number
#define XLLP_UDC_UDCCRZ_CN_SHIFT    25
#define XLLP_UDC_UDCCRZ_CN_MASK     ( 0x3U << XLLP_UDC_UDCCRZ_CN_SHIFT)    // Configuration Number