xllp_uart.c

PXA270硬件测试源代码

/******************************************************************************
**
**  COPYRIGHT (C) 2001, 2002 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:   xllp_Uart_funcs.c
**
**  PURPOSE:  Defines the low-level primitives that access the Bluetooth
**                  UART registers
**  
**
******************************************************************************/


#include "xllp_defs.h"
#include "xllp_serialization.h"
#include "xllp_gpio.h"
#include "xllp_clkmgr.h"
#include "xllp_bcr.h"
#include "xllp_uart.h"

void XllpUartInit(P_XLLP_UART_HANDLE_T pUARTHandle)
{
	XLLP_UINT32_T       LockID; // needed by XLLP serialization functions
    XLLP_VUINT32_T      temp;   // lvalue for flushing registers.
    XLLP_UINT32_T aGpioPinArray[9]; // a maximum array size of 9 is needed.
	XLLP_UINT32_T aAfValueArray[9];	// a maximum array size of 9 is needed.
	
    // UART, Clock Manager, BCR, and GPIO register pointers.
    P_XLLP_UART_T       pUARTRegs   =  pUARTHandle->pUARTRegs;
    P_XLLP_CLKMGR_T     pClkMgrRegs =  pUARTHandle->pCLKMGRRegs;
    P_XLLP_GPIO_T       pGPIORegs   =  pUARTHandle->pGPIORegs;
    P_XLLP_BCR_T        pBCRRegs    =  pUARTHandle->pBCRRegs;
    
    // Configure the UART registers to Reset Values.
    //  Ignore TBR, IIR, FOR, and ACR.
    pUARTRegs->LCR = 0;             // Access the IER Register, and force reset value.
    pUARTRegs->IER_DLH = 0;         // IER UART Unit Enable bit is cleared.
    pUARTRegs->IIR_FCR = (XLLP_FCR_RESETRF + XLLP_FCR_RESETTF);   // Reset TX and RX FIFOs.
    pUARTRegs->SPR = 0;             // SPR reset value.
    temp = pUARTRegs->RBR_THR_DLL;  // read RBR to empty.
    temp = pUARTRegs->LSR;          // read LSR to clear status bits.
    temp = pUARTRegs->MSR;          // read MSR to clear status bits.

	// Configure the GPIOs for FF or BT or STUART
    switch (pUARTHandle->UARTSelection)
    {
    case XLLP_FFUART:

        // Set Output signals high in Pin-Output Set Register.
		aGpioPinArray [0] = 3;	// Length = 3 for pins 39, 40, and 41.
		aGpioPinArray [1] = XLLP_GPIO_FFTXD; // pin 39
		aGpioPinArray [2] = XLLP_GPIO_FFDTR; // pin 40
		aGpioPinArray [3] = XLLP_GPIO_FFRTS; // pin 41	
		
        LockID = XllpLock(GPSR1); 					
		XllpGpioSetOutputState1 (pGPIORegs, aGpioPinArray); // Call XLLP function
     	XllpUnlock(LockID);	  
     	 
     	// Clear input bits in Pin-Direction Register.
		aGpioPinArray [0] = 5;	// Length = 5 for pins 34,35,37,36,38
		aGpioPinArray [1] = XLLP_GPIO_FFRXD; // pin 34
		aGpioPinArray [2] = XLLP_GPIO_FFCTS; // pin 35
		aGpioPinArray [3] = XLLP_GPIO_FFDSR; // pin 37	
		aGpioPinArray [4] = XLLP_GPIO_FFDCD; // pin 36
		aGpioPinArray [5] = XLLP_GPIO_FFRI;  // pin 38	
		
     	LockID = XllpLock(GPDR1);							
		XllpGpioSetDirectionIn (pGPIORegs, aGpioPinArray); // Call XLLP function                              
     	XllpUnlock(LockID);	
     	                              
        // Set output bits in Pin-Direction Register.
  		aGpioPinArray [0] = 3;	// Length = 3 for pins 39, 40, and 41.
		aGpioPinArray [1] = XLLP_GPIO_FFTXD; // pin 39
		aGpioPinArray [2] = XLLP_GPIO_FFDTR; // pin 40
		aGpioPinArray [3] = XLLP_GPIO_FFRTS; // pin 41				

     	LockID = XllpLock(GPDR1);
		XllpGpioSetDirectionOut (pGPIORegs, aGpioPinArray); // Call XLLP function
     	XllpUnlock(LockID);	
     	
        // Set FF fields in the Alternate Function Register.                                       
		aGpioPinArray [0] = 8;	// Length = 8 for pins 34-41
		aGpioPinArray [1] = XLLP_GPIO_FFRXD; // pin 34
		aGpioPinArray [2] = XLLP_GPIO_FFCTS; // pin 35
		aGpioPinArray [3] = XLLP_GPIO_FFDCD; // pin 36	
		aGpioPinArray [4] = XLLP_GPIO_FFDSR; // pin 37
		aGpioPinArray [5] = XLLP_GPIO_FFRI;  // pin 38
		aGpioPinArray [6] = XLLP_GPIO_FFTXD; // pin 39	
		aGpioPinArray [7] = XLLP_GPIO_FFDTR; // pin 40
		aGpioPinArray [8] = XLLP_GPIO_FFRTS; // pin 41
		
		aAfValueArray [0] = 8;	// Length = 8 for pins 34-41
		aAfValueArray [1] = XLLP_GPIO_AF_FFRXD; // pin 34
		aAfValueArray [2] = XLLP_GPIO_AF_FFCTS; // pin 35
		aAfValueArray [3] = XLLP_GPIO_AF_FFDCD; // pin 36	
		aAfValueArray [4] = XLLP_GPIO_AF_FFDSR; // pin 37
		aAfValueArray [5] = XLLP_GPIO_AF_FFRI;  // pin 38
		aAfValueArray [6] = XLLP_GPIO_AF_FFTXD; // pin 39	
		aAfValueArray [7] = XLLP_GPIO_AF_FFDTR; // pin 40
		aAfValueArray [8] = XLLP_GPIO_AF_FFRTS; // pin 41		
		
        LockID = XllpLock(GAFR1_L); 		
		XllpGpioSetAlternateFn (pGPIORegs, aGpioPinArray, aAfValueArray); // Call XLLP function
     	XllpUnlock(LockID);	      	
	    break;

    case XLLP_BTUART: // For BT only support CTS and RTS modem control pins
    
        // Set Output signals high in Pin-Output Set Register.
		aGpioPinArray [0] = 2;	// Length = 2 for pins 43, and 45.
		aGpioPinArray [1] = XLLP_GPIO_BTTXD; // pin 43
		aGpioPinArray [2] = XLLP_GPIO_BTRTS; // pin 45	
		
        LockID = XllpLock(GPSR1); 	
		XllpGpioSetOutputState1 (pGPIORegs, aGpioPinArray); // Call XLLP function                             
     	XllpUnlock(LockID);	  
     	
     	// Clear input bits in Pin-Direction Register.
  		aGpioPinArray [0] = 2;	// Length = 2 for pins 42, and 44.
		aGpioPinArray [1] = XLLP_GPIO_BTRXD; // pin 42
		aGpioPinArray [2] = XLLP_GPIO_BTCTS; // pin 44	
		
     	LockID = XllpLock(GPDR1); 					
		XllpGpioSetDirectionIn (pGPIORegs, aGpioPinArray); // Call XLLP function  
     	XllpUnlock(LockID);	
		                              
        // Set output bits in Pin-Direction Register.
  		aGpioPinArray [0] = 2;	// Length = 3 for pins 43, and 45.
		aGpioPinArray [1] = XLLP_GPIO_BTTXD; // pin 43
		aGpioPinArray [2] = XLLP_GPIO_BTRTS; // pin 45				
		
     	LockID = XllpLock(GPDR1); 
		XllpGpioSetDirectionOut (pGPIORegs, aGpioPinArray); // Call XLLP function                                                     
     	XllpUnlock(LockID);	
     	
        // Set BT fields in the Alternate Function Register.                                  
		aGpioPinArray [0] = 4;	// Length = 4 for pins 42-45
		aGpioPinArray [1] = XLLP_GPIO_BTRXD; // pin 42
		aGpioPinArray [2] = XLLP_GPIO_BTTXD; // pin 43
		aGpioPinArray [3] = XLLP_GPIO_BTCTS; // pin 44	
		aGpioPinArray [4] = XLLP_GPIO_BTRTS; // pin 45
		
		aAfValueArray [0] = 4;	// Length = 4 for pins 42-45
		aAfValueArray [1] = XLLP_GPIO_AF_BTRXD; // pin 42
		aAfValueArray [2] = XLLP_GPIO_AF_BTTXD; // pin 43
		aAfValueArray [3] = XLLP_GPIO_AF_BTCTS; // pin 44	
		aAfValueArray [4] = XLLP_GPIO_AF_BTRTS; // pin 45
		
        LockID = XllpLock(GAFR1_L); 
		XllpGpioSetAlternateFn (pGPIORegs, aGpioPinArray, aAfValueArray); // Call XLLP function		                               
     	XllpUnlock(LockID);	      	
	    break;

    case XLLP_STUART: // ST does not support any modem control capability
        // Set Output signals high in Pin-Output Set Register.
		aGpioPinArray [0] = 1;	// Length = 1 for pin 47.
		aGpioPinArray [1] = XLLP_GPIO_STD_TXD; // pin 47
		
        LockID = XllpLock(GPSR1); 		
		XllpGpioSetOutputState1 (pGPIORegs, aGpioPinArray); // Call XLLP function         
     	XllpUnlock(LockID);	  
     	

     	// Clear input bits in Pin-Direction Register.
  		aGpioPinArray [0] = 1;	// Length = 1 for pin 46.
		aGpioPinArray [1] = XLLP_GPIO_STD_RXD; // pin 46
		
     	LockID = XllpLock(GPDR1);  
		XllpGpioSetDirectionIn (pGPIORegs, aGpioPinArray); // Call XLLP function      	       
     	XllpUnlock(LockID);	
     	
        // Set output bits in Pin-Direction Register.
  		aGpioPinArray [0] = 1;	// Length = 1 for pin 47.
		aGpioPinArray [1] = XLLP_GPIO_STD_TXD; // pin 47
		
     	LockID = XllpLock(GPDR1);         
		XllpGpioSetDirectionOut (pGPIORegs, aGpioPinArray); // Call XLLP function      	
     	XllpUnlock(LockID);	
     	
        // Set FF fields in the Alternate Function Register.                                  
		aGpioPinArray [0] = 2;	// Length = 2 for pins 46, and 47
		aGpioPinArray [1] = XLLP_GPIO_STD_RXD; // pin 46
		aGpioPinArray [2] = XLLP_GPIO_STD_TXD; // pin 47
		
		aAfValueArray [0] = 2;	// Length = 2 for pins 46, and 47
		aAfValueArray [1] = XLLP_GPIO_AF_STD_RXD; // pin 46
		aAfValueArray [2] = XLLP_GPIO_AF_STD_TXD; // pin 47
		
        LockID = XllpLock(GAFR1_L); 
		XllpGpioSetAlternateFn (pGPIORegs, aGpioPinArray, aAfValueArray); // Call XLLP function		                               
     	XllpUnlock(LockID);	       	
	    break;
    	        	    
	default: // do nothing
	    break;
	}

    // Configure the BCR Miscellaneous Write Register 1 to user specified values.
    LockID = XllpLock(MISC_WR);
    switch (pUARTHandle->UARTSelection)
    {
    case XLLP_BTUART: // If BT then allow only the Bluetooth fields to be modified
        pBCRRegs->MISCWR1 &= ~(XLLP_BCR_MISCWR1_BTDTR + XLLP_BCR_MISCWR1_nBT_OFF ); 
        pBCRRegs->MISCWR1 |= pUARTHandle->BCR_MISCWR1_Value & (XLLP_BCR_MISCWR1_BTDTR +
                             XLLP_BCR_MISCWR1_nBT_OFF );
	    break;
    case XLLP_STUART: // if ST then allow only IRDA fields to be modified
    pBCRRegs->MISCWR1 &= ~(XLLP_BCR_MISCWR1_IRDA_FIR + XLLP_BCR_MISCWR1_IRDA_MD); 
    pBCRRegs->MISCWR1 |= pUARTHandle->BCR_MISCWR1_Value & (XLLP_BCR_MISCWR1_IRDA_FIR +
                         XLLP_BCR_MISCWR1_IRDA_MD);
	    break;	
    case XLLP_FFUART: // do nothing to BCR
	default: // do nothing
	    break;
	}
  	XllpUnlock(LockID);

	// Configure the Clock Manager for FF or BT or STUART
    LockID = XllpLock(CKEN);
    switch (pUARTHandle->UARTSelection)
    {
    case XLLP_FFUART:
	    pClkMgrRegs->cken |= XLLP_CLKEN_FFUART;
	    break;
    case XLLP_BTUART:
	    pClkMgrRegs->cken |= XLLP_CLKEN_BTUART;
	    break;
    case XLLP_STUART:
	    pClkMgrRegs->cken |= XLLP_CLKEN_STUART;
	    break;	    	    
	default: // do nothing
	    break;
	}
	XllpUnlock(LockID);
 
    // Set Baud Rate.
    pUARTRegs->LCR = XLLP_LCR_DLAB;      // Access the DLL and DLH Registers.
    pUARTRegs->RBR_THR_DLL = pUARTHandle->DLL_Value; 
    pUARTRegs->IER_DLH = pUARTHandle->DLH_Value;
        
    // Set LCR to user specified values.
    // Note Divisor Latch Access Bit, and Set Break fields are always cleared.
    pUARTRegs->LCR = pUARTHandle->LCR_Value & (XLLP_LCR_STKYP + XLLP_LCR_EPS + 
                     XLLP_LCR_PEN + XLLP_LCR_STB + XLLP_LCR_WLS8);  
                         
    // Set FCR to user specified values.
    // Note RESETRF and RESETTF fields can't be modified, but they were set earlier 
    // in this function.
    pUARTRegs->IIR_FCR = pUARTHandle->FCR_Value & (XLLP_FCR_ITL32 + XLLP_FCR_BUS + 
                                                   XLLP_FCR_TRAIL + XLLP_FCR_TIL + 
                                                   XLLP_FCR_TRFIFOE);

    // Set ABR to user specified values.
    pUARTRegs->ABR = pUARTHandle->ABR_Value & (XLLP_ABR_ABT + XLLP_ABR_ABUP + 
                                               XLLP_ABR_ABLIE + XLLP_ABR_ABE);
    
    // Set MCR to user specified values.
    pUARTRegs->MCR = pUARTHandle->MCR_Value & (XLLP_MCR_AFE + XLLP_MCR_LOOP + 
                                               XLLP_MCR_OUT2 + XLLP_MCR_RTS + 
                                               XLLP_MCR_DTR);

    // Set ISR to user specified values.
    pUARTRegs->ISR = pUARTHandle->ISR_Value & (XLLP_ISR_XMITIR + XLLP_ISR_RCVEIR + 
                                               XLLP_ISR_XMODE + XLLP_ISR_TXPL + 
                                               XLLP_ISR_RXPL);

    // Set IER to user specified values.
    pUARTRegs->IER_DLH = pUARTHandle->IER_Value & (XLLP_IER_DMAE + XLLP_IER_UUE + 
                                                   XLLP_IER_NRZE + XLLP_IER_RTOIE + 
                                                   XLLP_IER_MIE + XLLP_IER_RLSE +
                                                   XLLP_IER_TIE + XLLP_IER_RAVIE );
     
}// end of XllpUartConfigure()