xllp_wm9712.h

PXA270硬件测试源代码

#define XLLP_AC97_U14_ICSR_TSMX   ( 0x1 << 13 )   // use to check or clear the int status for TSMX
#define XLLP_AC97_U14_ICSR_D14    ( 0x1 << 14 )   // Reserved
#define XLLP_AC97_U14_ICSR_OVLS   ( 0x1 << 15 )   // use to check or clear the int status for OVFL

// Touch Screen Control Register (TSCR) defintions

#define XLLP_AC97_U14_TSCR_TSMX_POW   ( 0x1 << 0 )    // TSMX pin is powered
#define XLLP_AC97_U14_TSCR_TSPX_POW   ( 0x1 << 1 )    // TSPX pin is powered
#define XLLP_AC97_U14_TSCR_TSMY_POW   ( 0x1 << 2 )    // TSMY pin is powered
#define XLLP_AC97_U14_TSCR_TSPY_POW   ( 0x1 << 3 )    // TSPY pin is powered

#define XLLP_AC97_U14_TSCR_TSMX_GND   ( 0x1 << 4 )    // TSMX pin is grounded
#define XLLP_AC97_U14_TSCR_TSPX_GND   ( 0x1 << 5 )    // TSPX pin is grounded
#define XLLP_AC97_U14_TSCR_TSMY_GND   ( 0x1 << 6 )    // TSMY pin is grounded
#define XLLP_AC97_U14_TSCR_TSPY_GND   ( 0x1 << 7 )    // TSPY pin is grounded

#define XLLP_AC97_U14_TSCR_INTMO      ( 0x0 << 8 )    // Interrupt Mode
#define XLLP_AC97_U14_TSCR_PREMO      ( 0x1 << 8 )    // Pressure Measurement Mode
#define XLLP_AC97_U14_TSCR_POSMO      ( 0x2 << 8 )    // Position Measurement Mode
#define XLLP_AC97_U14_TSCR_HYSD       ( 0x1 << 10 )   // Hysteresis deactivated
#define XLLP_AC97_U14_TSCR_BIAS       ( 0x1 << 11 )   // Bias circuitry activated

#define XLLP_AC97_U14_TSCR_PX         ( 0x1 << 12 )   // Inverted state of TSPX pin
#define XLLP_AC97_U14_TSCR_MX         ( 0x1 << 13 )   // Inverted state of TSMX pin
#define XLLP_AC97_U14_TSCR_D14        ( 0x1 << 14 )   // Reserved
#define XLLP_AC97_U14_TSCR_D15        ( 0x1 << 15 )   // Reserved

// ADC Control Register (ADCCR) definitions

#define XLLP_AC97_U14_ADCCR_ASE       ( 0x1 << 0 ) // ADC is armed by AS bit and started by rising edge on ADCSYNC pin
#define XLLP_AC97_U14_ADCCR_D1        ( 0x1 << 1 ) // Reserved

#define XLLP_AC97_U14_ADCCR_AI_SHIFT  2
#define XLLP_AC97_U14_ADCCR_AI_TSPX   ( 0x0 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is TSPX
#define XLLP_AC97_U14_ADCCR_AI_TSMX   ( 0x1 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is TSMX
#define XLLP_AC97_U14_ADCCR_AI_TSPY   ( 0x2 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is TSPY
#define XLLP_AC97_U14_ADCCR_AI_TSMY   ( 0x3 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is TSMY
#define XLLP_AC97_U14_ADCCR_AI_AD0    ( 0x4 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is AD0
#define XLLP_AC97_U14_ADCCR_AI_AD1    ( 0x5 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is AD1
#define XLLP_AC97_U14_ADCCR_AI_AD2    ( 0x6 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is AD2
#define XLLP_AC97_U14_ADCCR_AI_AD3    ( 0x7 << XLLP_AC97_U14_ADCCR_AI_SHIFT )   // ADC source is AD3

#define XLLP_AC97_U14_ADCCR_D5        ( 0x1 << 5 )    // Reserved
#define XLLP_AC97_U14_ADCCR_D6        ( 0x1 << 6 )    // Reserved
#define XLLP_AC97_U14_ADCCR_AS        ( 0x1 << 7 )    // Start the ADC conversion seq.

#define XLLP_AC97_U14_ADCCR_D8        ( 0x1 << 8 )    // Reserved
#define XLLP_AC97_U14_ADCCR_D9        ( 0x1 << 9 )    // Reserved
#define XLLP_AC97_U14_ADCCR_D10       ( 0x1 << 10 )   // Reserved
#define XLLP_AC97_U14_ADCCR_D11       ( 0x1 << 11 )   // Reserved

#define XLLP_AC97_U14_ADCCR_D12       ( 0x1 << 12 )   // Reserved
#define XLLP_AC97_U14_ADCCR_D13       ( 0x1 << 13 )   // Reserved
#define XLLP_AC97_U14_ADCCR_D14       ( 0x1 << 14 )   // Reserved
#define XLLP_AC97_U14_ADCCR_AE        ( 0x1 << 15 )   // ADC is activated

// ADC Data Register (ADCDR) definitions

#define XLLP_AC97_U14_ADCDR_MASK      0x3FF           // ADC data register data mask
#define XLLP_AC97_U14_ADCDR_ADV       ( 0x1 << 15 )   // Conversion complete

// Feature Control/Status Register 1 (FCSR1) definitions

#define XLLP_AC97_U14_FCSR1_OVFL      ( 0x1 << 0 )    // ADC overflow status
// bit 1 is reserved
#define XLLP_AC97_U14_FCSR1_GIEN      ( 0x1 << 2 )    // Enable interrupt/wakeup signaling
#define XLLP_AC97_U14_FCSR1_HIPS      ( 0x1 << 3 )    // Activate ADC High Pass Filter
#define XLLP_AC97_U14_FCSR1_DC        ( 0x1 << 4 )    // DC filter is enabled
#define XLLP_AC97_U14_FCSR1_DE        ( 0x1 << 5 )    // De-emphasis is enabled
#define XLLP_AC97_U14_FCSR1_XTM       ( 0x1 << 6 )    // Crystal Oscillator Powerdown Mode

#define XLLP_AC97_U14_FCSR1_M_SHIFT   7
#define XLLP_AC97_U14_FCSR1_M_FLAT    ( 0x00 << XLLP_AC97_U14_FCSR1_M_SHIFT )   // Flat mode
#define XLLP_AC97_U14_FCSR1_M_MIN1    ( 0x1 << XLLP_AC97_U14_FCSR1_M_SHIFT )    // Minimum mode
#define XLLP_AC97_U14_FCSR1_M_MIN2    ( 0x2 << XLLP_AC97_U14_FCSR1_M_SHIFT )    // Minimum mode
#define XLLP_AC97_U14_FCSR1_M_MAX     ( 0x3 << XLLP_AC97_U14_FCSR1_M_SHIFT )    // Maximum mode

#define XLLP_AC97_U14_FCSR1_TR_SHIFT  9   // 2 bits wide, Treble Boost

#define XLLP_AC97_U14_FCSR1_BB_SHIFT  11  // 4 bits wide, Bass Boost
// Bit 15 Reserved

// Feature Control/Status Register 2 (FCSR2) definitions

#define XLLP_AC97_U14_FCSR2_EV_SHIFT   0
#define XLLP_AC97_U14_FCSR2_EV_MASK    ( 0x7 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Mask for reading or clearing EV */
#define XLLP_AC97_U14_FCSR2_EV_NORMOP  ( 0x0 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for normal operation
#define XLLP_AC97_U14_FCSR2_EV_ACLPBK  ( 0x1 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for ACLink loopback
#define XLLP_AC97_U14_FCSR2_EV_BSLPBK  ( 0x2 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for bitstr loopback
#define XLLP_AC97_U14_FCSR2_EV_DACEVAL ( 0x3 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for DAC bitstr eval
#define XLLP_AC97_U14_FCSR2_EV_ADCEVAL ( 0x4 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for ADC bitstr eval
#define XLLP_AC97_U14_FCSR2_EV_CLKEVAL ( 0x5 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for Clocks eval mode
#define XLLP_AC97_U14_FCSR2_EV_ADC10EV ( 0x6 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for 10 bit ADC eval mode
#define XLLP_AC97_U14_FCSR2_EV_NORMOP1 ( 0x7 << XLLP_AC97_U14_FCSR2_EV_SHIFT ) // Set EV for normal operation
// Bit 3 Reserved

#define XLLP_AC97_U14_FCSR2_SLP_SHIFT     4
#define XLLP_AC97_U14_FCSR2_SLP_MASK      ( 0x3 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // Mask for reading or clearing SLP
#define XLLP_AC97_U14_FCSR2_SLP_NSLP      ( 0x0 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // No Smart Low Power Mode
#define XLLP_AC97_U14_FCSR2_SLP_SLPC      ( 0x1 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // Smart Low Power Codec
#define XLLP_AC97_U14_FCSR2_SLP_SLPPLL    ( 0x2 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // Smart Low Power PLL
#define XLLP_AC97_U14_FCSR2_SLP_SLPALL    ( 0x3 << XLLP_AC97_U14_FCSR2_SLP_SHIFT )  // Smart Low Power Codec & PLL
// Bits 6-15 Reserved

// Test Control Register (TCR) definitions
#define XLLP_AC97_U14_TCR_IDDQ    ( 0x1 << 0 )    // IDDQ testing
#define XLLP_AC97_U14_TCR_ROM     ( 0x1 << 1 )    // ROM testing
#define XLLP_AC97_U14_TCR_RAM     ( 0x1 << 2 )    // RAM testing
#define XLLP_AC97_U14_TCR_VOH     ( 0x1 << 3 )    // VOH testing
#define XLLP_AC97_U14_TCR_VOL     ( 0x1 << 4 )    // VOL testing
#define XLLP_AC97_U14_TCR_TRI     ( 0x1 << 5 )    // Tri-Sate testing
// Bits 7-15 Reserved


#define XLLP_AC97_U14_MAX_VOLUME    63
#define XLLP_AC97_U14_MAX_ADCGAIN   15

//9712 specific
//		Register Name			Index			// Usage
//-----------------------------------------------------------------------
#define RESET					0X00			// RESET CODEC TO DEFAULT					
#define MASTER_VOLUME			0X02			// LINE OUT VOLUME
#define LOUT2_ROUT2 			0X02			// 9712
#define HEADPHONE_VOLUME		0X04
#define MASTER_VOLUME_MONO		0X06
#define MONOOUT_VOLUME  		0X06			// 9712
#define DAC_TONE_CONT			0X08
#define MASTER_TONE_R_L			0X08			// 9712
#define PC_BEEP_VOLUME			0X0A
#define PHONE_VOLUME			0X0C
#define MIC_VOLUME				0X0E			// MICROPHONE VOLUME/ AGC
#define LINE_IN_VOLUME			0X10			// LINE IN VOLUME
#define CD_VOLUME				0X12
#define AUX_ADC_VOL_ROUT		0X12			// 9712
#define VIDEO_VOLUME			0X14
#define SIDETONE_VOLUME			0X14			// 9712
#define AUX_VOLUME				0X16
#define OUT3_VOLUME 			0X16			// 9712
#define PCM_OUT_VOL				0X18
#define DAC_VOLUME				0X18			// 9712
#define RECORD_SELECT			0X1A			// SELECT LINE IN OR MICROPHONE
#define RECORD_GAIN				0X1C
#define RECORD_GAIN_MIC			0X1E			//undefined for UCB1400
#define GENERAL_PURPOSE			0X20
#define CONTROL_3D				0X22
#define RESERVED				0X24
#define POWERDOWN_CTRL_STAT		0X26			// POWER MANAGEMENT
#define EXTENDED_AUDIO_ID		0X28
#define EXTENDED_AUDIO_CTRL		0X2A			// BIT 0 must be set to 1 for variable rate audio
#define AUDIO_DAC_RATE			0X2C			// 16 bit unsigned is sample rate in hertz
#define AUDIO_ADC_RATE			0X32			// 16 bit unsigned is sample rate in hertz
#define SPDIF					0X3A			
#define GPIO_PIN_CFG			0X4C			
#define GPIO_PIN_POL_TYPE		0X4E			
#define GPIO_PIN_STICKY 		0X50			
#define GPIO_PIN_WAKEUP			0X52			
#define GPIO_PIN_STATUS			0X54			
#define GPIO_PIN_ASSIGN			0X56			
#define GPIO_PIN_SHARE_ADD		0X58			
#define ADD_FUNC         		0X5C			
#define ALC_CTRL         		0X60			
#define ALC_NOISE_GATE     		0X62			
#define AUX_DAC_INPUT      		0X64			
#define FEATURE_CSR1			0x6A			// UCB1400 specific bass, treble and other items
#define FEATURE_CSR2			0x6C			// UCB1400 specific bass, treble and other items
#define DIGITIZER_1	  		    0x76			// 9712
#define DIGITIZER_2	  		    0x78			// 9712
#define DIGITIZER_READ 		    0x7a			// 9712
#define VENDOR_ID1	  		    0x7c			// UCB1400 id first 16 bits
#define VENDOR_ID2	  		    0x7e			// UCB1400 id second 16 bits

#define VRA_ENABLED_MASK		0x1				// VRA bit set to 1 enables sample rate conversion



/*WM9712 related functions*/
extern XLLP_ACODEC_ERROR_T XllpWm9712SetMasterVol(XLLP_ACODEC_CONTEXT_T *pDeviceContext,unsigned short int GainInDb);
extern XLLP_ACODEC_ERROR_T XllpWm9712SetMasterInputGain(XLLP_ACODEC_CONTEXT_T *pDeviceContext,unsigned short int GainInDb);
extern XLLP_ACODEC_ERROR_T XllpWm9712GetInSampleRate(XLLP_ACODEC_CONTEXT_T *pDeviceContext,unsigned short int * RateInKhz);
extern XLLP_ACODEC_ERROR_T XllpWm9712GetOutSampleRate (XLLP_ACODEC_CONTEXT_T *pDeviceContext,unsigned short int * RateInKhz);
extern XLLP_ACODEC_ERROR_T XllpWm9712SetInSampleRate(XLLP_ACODEC_CONTEXT_T *pDeviceContext,unsigned short int RateInKhz);
extern XLLP_ACODEC_ERROR_T XllpWm9712SetOutSampleRate (XLLP_ACODEC_CONTEXT_T *pDeviceContext,unsigned short int RateInKhz);
extern XLLP_ACODEC_ERROR_T XllpWm9712EnterEquipmentState (XLLP_ACODEC_CONTEXT_T *pDeviceContext,XLLP_ACODEC_EQUIPMENT_T equipmentState);
extern XLLP_ACODEC_ERROR_T XllpWm9712GetEquipmentState (XLLP_ACODEC_CONTEXT_T *pDeviceContext,XLLP_ACODEC_EQUIPMENT_T * pEquipmentState);	
extern XLLP_ACODEC_ERROR_T XllpWm9712SpecificInit (XLLP_ACODEC_CONTEXT_T *pDeviceContext);
extern XLLP_ACODEC_ERROR_T XllpWm9712SpecificDeInit (XLLP_ACODEC_CONTEXT_T *pDeviceContext);




#endif