📄 xllp_dmac.h
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XLLP_DMAC_BASEBAND_6_RX,
XLLP_DMAC_BASEBAND_6_TX,
XLLP_DMAC_BASEBAND_7_RX,
XLLP_DMAC_BASEBAND_7_TX,
XLLP_DMAC_USIM_RX,
XLLP_DMAC_USIM_TX,
XLLP_DMAC_MEMORY_STICK_RX,
XLLP_DMAC_MEMORY_STICK_TX,
XLLP_DMAC_SSP_3_RX,
XLLP_DMAC_SSP_3_TX,
XLLP_DMAC_MEM2MEM_MOVE = 99 /* RESERVED for Memory to Memory moves */
}XLLP_DMAC_DRCMR_T, XLLP_DMAC_DEVICE_T;
/**
* DMAC Interrupts
**/
typedef enum
{
XLLP_DMAC_BUS_ERR_INT = 0,
XLLP_DMAC_START_INT,
XLLP_DMAC_END_INT,
XLLP_DMAC_STOP_INT,
XLLP_DMAC_EOR_INT = 9
}XLLP_DMAC_INTERRUPT_T;
/**
* DMAC Transfer Type
**/
typedef enum
{
XLLP_DMAC_TRANSFER_MEM_TO_MEM = 0,
XLLP_DMAC_TRANSFER_IO_TO_MEM,
XLLP_DMAC_TRANSFER_MEM_TO_IO
}XLLP_DMAC_TRANSFER_TYPE_T;
/**
* DMAC Transfer Mode
**/
typedef enum
{
XLLP_DMAC_DESCRIPTOR_MODE = 0,
XLLP_DMAC_NO_DESCRIPTOR_MODE
}XLLP_DMAC_TRANSFER_MODE_T;
/**
* DMAC Descriptor Branching Mode
**/
typedef enum
{
XLLP_DMAC_DISABLE_DESC_BRANCH = 0,
XLLP_DMAC_ENABLE_DESC_BRANCH
}XLLP_DMAC_DESC_BRANCH_T;
/**
* DMAC Descriptor Enable
**/
typedef enum
{
XLLP_DMAC_DESC_RUN_CHANNEL = 0,
XLLP_DMAC_DESC_STOP_CHANNEL
}XLLP_DMAC_DESC_ENABLE_T;
/**
* DMA Command
**/
typedef struct
{
XLLP_INT16_T aLen; // Length of transfer in bytes. Max 0x1FFF
XLLP_DMAC_DEVICE_WIDTH_T aWidth; // Width of on-chip peripheral
XLLP_DMAC_DEVICE_BURSTSIZE_T aSize; // Max. burst size of each data transferred
XLLP_BOOL_T aEndian; // Device endianness. 0=Little, 1=Big endian
XLLP_BOOL_T aFlyByT; // Fly-By target bit
XLLP_BOOL_T aFlyByS; // Fly-By source bit
XLLP_BOOL_T aEndIrqEn; // End Interrupt Enable. When set,
// generate interrupt when aLen=0
XLLP_BOOL_T aStartIrqEn; // Start Int. enable. When set, generate
// interrupt after loading descriptor.
// Reserved for No Descriptor Mode Xfer
XLLP_BOOL_T aAddrMode; // Addressing mode for descriptor comparison
XLLP_BOOL_T aCmpEn; // Descriptor compare enable bit
XLLP_BOOL_T aFlowTrg; // Flow control of the target.
XLLP_BOOL_T aFlowSrc; // Flow control of the source
XLLP_BOOL_T aIncTrgAddr; // Target address increment setting
XLLP_BOOL_T aIncSrcAddr; // Source address increment setting
}XLLP_DMAC_COMMAND_T, *P_XLLP_DMAC_COMMAND_T;
/**
* DMAC Channel Status
**/
typedef enum
{
XLLP_DMAC_STATUS_BUSERRINTR = 0, // Bus error causing int.
XLLP_DMAC_STATUS_STARTINTR, // Successful Descriptor fetch int.
XLLP_DMAC_STATUS_ENDINTR, // Successful completion int.
XLLP_DMAC_STATUS_STOPINTR, // Channel state, 0=Running, 1=Stop
XLLP_DMAC_STATUS_REQPEND = 8, // Channel Request pending state.
// 1=Channel has pending req, 0=No Req
XLLP_DMAC_STATUS_EORINT, // Indicates status of peripheral Rx data
XLLP_DMAC_STATUS_CMPST // Descriptor compare status
}XLLP_DMAC_CHANNEL_STATUS_T, *P_XLLP_DMAC_CHANNEL_STATUS_T;
/**
* DMAC External Request Pins
**/
typedef enum
{
XLLP_DMAC_EXTERNAL_PIN_0 = 0,
XLLP_DMAC_EXTERNAL_PIN_1
}XLLP_DMAC_EXT_PIN_T;
/**
* DMAC Data Alignment
**/
typedef enum
{
XLLP_DMAC_ALIGNMENT_OFF = 0,
XLLP_DMAC_ALIGNMENT_ON
}XLLP_DMAC_ALIGNMENT_T;
/**
* DMAC Channel Allocation Priority
**/
typedef enum
{
XLLP_DMAC_CHANNEL_PRIORITY_HIGH = 0,
XLLP_DMAC_CHANNEL_PRIORITY_MEDIUM,
XLLP_DMAC_CHANNEL_PRIORITY_LOW,
XLLP_DMAC_CHANNEL_PRIORITY_LOWEST
}XLLP_DMAC_CHANNEL_PRIORITY_T;
#define XLLP_DMAC_DDADR_RESERVED_MASK 0xFFFFFFF0
#define XLLP_DMAC_DRCMR_ENABLE 0x80
#define XLLP_DMAC_DRCMR_DISABLE 0x00
/**
* Represents a contiguous physical block of memory
**/
typedef struct _PhysBlock
{
XLLP_UINT32_T physicalAds; // Array of physical addresses of each contigious physical block
XLLP_UINT32_T blockLength; // Length of each contigious block
} PhysBlock, *PPhysBlock;
/**
* A Memory Descriptor List (MDL) structure
* This stores information about physical mappings of a buffer
**/
typedef struct _BufferMdl
{
XLLP_UINT32_T numEntries; // Number of entries of physical blocks representing this buffer
XLLP_UINT8_T* bufferPtr; // Virtual Buffer ptr
PhysBlock *physBlock; // Array of Physical blocks for buffer
} BufferMdl, *PBufferMdl;
/**
* This allows us to allocate descriptors and properly align them (on 16 byte boundaries) as well
**/
typedef struct _dmaDescInfo
{
XLLP_UINT8_T* memPtr; // Pointer to this block of memory
XLLP_UINT32_T numEntries; // Number of descriptors
P_XLLP_DMAC_DESCRIPTOR_T pDmaDescList; // Array of properly aligned DMA descriptors
} DmaDescInfo, *PDmaDescInfo;
/**
* Declaration for secondary handlers invoked by DMA interrupt handler at interrupt time
**/
typedef void (*DeviceDmaIntHandler) (void* userContext, XLLP_UINT32_T channelDcsr);
/**
* Information stored on a per DMA channel
**/
typedef struct _DmaChannelConfigInfo
{
XLLP_DMAC_DRCMR_T drcmrId;
DeviceDmaIntHandler pDeviceHandler; // Pointer to the client's interrupt handler for this channel.
void* pUserContext; // Pass back to registered handler
} DmaChannelConfigInfo,*PDmaChannelConfigInfo;
/**
* XLLP DMA Primitive Functions
**/
XLLP_STATUS_T XllpDmacAllocChannel(P_XLLP_DMAC_CHANNEL_T pChannel,
XLLP_DMAC_CHANNEL_PRIORITY_T aChannelPriority);
XLLP_STATUS_T XllpDmacAllocOneChannel(XLLP_DMAC_CHANNEL_T aChannel);
void XllpDmacFreeChannel(XLLP_DMAC_CHANNEL_T aChannel,
XLLP_DMAC_DEVICE_T aDevice);
void XllpDmacFillLinkedDesc(P_XLLP_DMAC_DESCRIPTOR_T pDesc,
P_XLLP_DMAC_DESCRIPTOR_T pNextDescPhyAddr,
XLLP_DMAC_DESC_ENABLE_T aStopContinue,
XLLP_DMAC_DESC_BRANCH_T aBranch,
XLLP_UINT32_T aSrcAddr,
XLLP_UINT32_T aTargetAddr,
XLLP_DMAC_COMMAND_T *pCmd);
void XllpDmacCfgChannelDescTransfer(P_XLLP_DMAC_DESCRIPTOR_T pDesc,
XLLP_DMAC_CHANNEL_T aChannel,
XLLP_DMAC_DEVICE_T aDevice,
XLLP_DMAC_ALIGNMENT_T aLignment);
void XllpDmacCfgChannelNoDescTransfer(XLLP_UINT32_T aSourcAddr,
XLLP_UINT32_T aTargetAddr,
XLLP_DMAC_COMMAND_T *pCmd,
XLLP_DMAC_CHANNEL_T aChannel,
XLLP_DMAC_DEVICE_T aDevice,
XLLP_DMAC_ALIGNMENT_T aLignment);
void XllpDmacStartTransfer(XLLP_DMAC_CHANNEL_T aChannel);
void XllpDmacStopTransfer(XLLP_DMAC_CHANNEL_T aChannel);
void XllpDmacAttachDesc(P_XLLP_DMAC_DESCRIPTOR_T pDesc,
P_XLLP_DMAC_DESCRIPTOR_T pPrevDesc,
P_XLLP_DMAC_DESCRIPTOR_T pNextDesc,
P_XLLP_DMAC_DESCRIPTOR_T pStartDesc,
XLLP_DMAC_CHANNEL_T aChannel);
void XllpDmacDetachDesc(P_XLLP_DMAC_DESCRIPTOR_T pDesc,
P_XLLP_DMAC_DESCRIPTOR_T pPrevDesc,
P_XLLP_DMAC_DESCRIPTOR_T pNextDesc,
P_XLLP_DMAC_DESCRIPTOR_T pStartDesc,
XLLP_DMAC_CHANNEL_T aChannel);
void XllpDmacGetChannelStatus(XLLP_DMAC_CHANNEL_T aChannel,
XLLP_DMAC_CHANNEL_STATUS_T aStatus,
P_XLLP_DMAC_CHANNEL_STATUS_T pStatus);
void XllpDmacClearChannelStatus(XLLP_DMAC_CHANNEL_T aChannel,
XLLP_DMAC_CHANNEL_STATUS_T aStatus );
void XllpDmacMapDeviceToChannel(XLLP_DMAC_DRCMR_T aDevice,
XLLP_DMAC_CHANNEL_T aChannel);
void XllpDmacUnMapDeviceToChannel(XLLP_DMAC_DRCMR_T aDevice,
XLLP_DMAC_CHANNEL_T aChannel);
// This is only needed when running without the XLLP DMA Engine.
XLLP_STATUS_T XllpDmacInitHandle(P_XLLP_DMAC_T address);
void XllpDmacHwInit(void);
XLLP_STATUS_T XllpDmacRegisterDeviceHandler(XLLP_DMAC_CHANNEL_T dmaChannel,
DeviceDmaIntHandler dmaIntHandler,
void* userContext);
XLLP_STATUS_T XllpDmacUnregisterDeviceHandler(XLLP_DMAC_CHANNEL_T dmaChannel);
XLLP_STATUS_T XllpDmacEnableInterrupts (XLLP_DMAC_CHANNEL_T dmaChannel,XLLP_UINT32_T interruptBitmask);
XLLP_STATUS_T XllpDmacDisableInterrupts(XLLP_DMAC_CHANNEL_T dmaChannel,XLLP_UINT32_T interruptBitmask);
void XllpDmacInterruptHandler(void);
XLLP_INT32_T XllpDmacGetRemainingXfrLength(XLLP_DMAC_CHANNEL_T dmaChannel);
XLLP_UINT32_T XllpDmacGetPhysicalAds(void* virtualAddress);
XLLP_STATUS_T XllpDmacCreateDescriptorListFromMdl( PBufferMdl pBufferMdl,
XLLP_DMAC_TRANSFER_TYPE_T transferType,
PDmaDescInfo *pDmaDescInfo,
XLLP_UINT32_T deviceAddress,
XLLP_DMAC_COMMAND_T *pCmd);
XLLP_STATUS_T XllpDmacCreateDescriptorList( XLLP_UINT8_T* pBuffer,
XLLP_UINT32_T bufferLength,
XLLP_DMAC_TRANSFER_TYPE_T transferType,
PDmaDescInfo *pDmaDescInfo,
XLLP_UINT32_T deviceAddress,
XLLP_DMAC_COMMAND_T *pCmd,
XLLP_DMAC_ALIGNMENT_T *aLign);
PDmaDescInfo XllpDmacAllocDmaDescriptorList(XLLP_UINT32_T numEntries);
void XllpDmacFreeDescriptorList (PDmaDescInfo pDmaDescInfo);
PBufferMdl XllpDmacAllocateMdl(XLLP_UINT32_T numEntries);
void XllpDmacFreeBufferMdl( XLLP_UINT8_T *pBuffer,
XLLP_UINT32_T bufferLength,
PBufferMdl pBufferMdl);
XLLP_STATUS_T XllpDmacCreateBufferMdl(XLLP_UINT8_T *pBuffer,
XLLP_UINT32_T bufferLength,
PBufferMdl *pBufferMdl,
XLLP_DMAC_ALIGNMENT_T *aLign);
XLLP_STATUS_T XllpDmacGetXfrDone( XLLP_DMAC_CHANNEL_T dmaChannel,
PBufferMdl pBufferMdl,
XLLP_DMAC_TRANSFER_TYPE_T transferType,
XLLP_UINT32_T *bytesXferred);
XLLP_STATUS_T XllpDmacSetupTransfer( XLLP_DMAC_CHANNEL_PRIORITY_T aChannelPriority,
XLLP_UINT8_T* pUserBuffer,
XLLP_UINT32_T xferByteCount,
XLLP_DMAC_TRANSFER_TYPE_T transferType,
XLLP_UINT32_T deviceAddress,
XLLP_DMAC_DEVICE_T aDeviceDrcmr,
DeviceDmaIntHandler dmaIntHandler,
void* pUserContext,
XLLP_UINT32_T intEnableBitmask,
XLLP_UINT32_T descBasedXfr,
XLLP_DMAC_COMMAND_T* pCmd,
XLLP_DMAC_CHANNEL_T* dmaChannel,
PDmaDescInfo* pUserDmaDescInfo,
PBufferMdl* pUserBufferMdl);
void XllpDmacEnableInterrupt(void);
void XllpDmacDisableInterrupt(void);
void XllpDmacDumpStatus( XLLP_DMAC_CHANNEL_T aChannel );
void XllpDmacSetEor ( XLLP_DMAC_CHANNEL_T aChannel );
#endif //__DMAC_H__
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