xllp_pmu.h

PXA270硬件测试源代码

/******************************************************************************
**
**  COPYRIGHT (C) 2001, 2002 Intel Corporation.
**
**  This software as well as the software described in it is furnished under
**  license and may only be used or copied in accordance with the terms of the
**  license. The information in this file is furnished for informational use
**  only, is subject to change without notice, and should not be construed as
**  a commitment by Intel Corporation. Intel Corporation assumes no
**  responsibility or liability for any errors or inaccuracies that may appear
**  in this document or any software that may be provided in association with
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by
**  any means without the express written consent of Intel Corporation. 
** 
**  FILENAME:       xllp_pmu.h
**
**	CORE STEPPING: Elkhardt 
**
**  PURPOSE: contains all PMU specific macros, typedefs, and prototypes.
**           Declares no storage.
**                  
**
******************************************************************************/

#ifndef __XLLP_PMU_H__
#define __XLLP_PMU_H__


#include "xllp_defs.h"



/* PMU Performance Monitor Control Register (PMNC) */
#define XLLP_PMU_ID							(0x14u << 24)
#define XLLP_PMU_CLOCK_DIVIDER				(XLLP_BIT_3)
#define XLLP_PMU_CLOCK_RESET				(XLLP_BIT_2)
#define XLLP_PMU_COUNTERS_RESET				(XLLP_BIT_1)
#define XLLP_PMU_3_COUNTERS_ENABLE			(XLLP_BIT_0)

#define XLLP_PMNC_RESERVED_BITS				(0xFFFFFFF0u)

/* INTEN & FLAG Registers bit definition*/
#define XLLP_PMU_CLOCK_COUNT				(XLLP_BIT_0)
#define XLLP_PMU_COUNT_0					(XLLP_BIT_1)
#define XLLP_PMU_COUNT_1					(XLLP_BIT_2)
#define XLLP_PMU_COUNT_2					(XLLP_BIT_3)
#define XLLP_PMU_COUNT_3					(XLLP_BIT_4)

#define XLLP_INTEN_FLAG_RESERVED_BITS		(0xFFFFFFE0u)

/*Events combination*/
/*evtCount0/2:0x7(instruction count), evtCount1/3:0x0(ICache miss)*/
#define XLLP_PMU_EVTCOUNT_1					(0x0007)
/*evtCount0/2:0xA(DCache Access), evtCount1/3:0xB(DCache miss)*/
#define XLLP_PMU_EVTCOUNT_2					(0x0B0A)
/*evtCount0/2:0x1(ICache cannot deliver), evtCount1/3:0x0(ICache miss)*/
#define XLLP_PMU_EVTCOUNT_3					(0x0001)
/*evtCount0/2:0xB(DBufer stall duration), evtCount1/3:0x9(Dbuffer stall)*/
#define XLLP_PMU_EVTCOUNT_4					(0x090B)
/*evtCount0/2:0x2(data stall), evtCount1/3:0xC(DCache writeback)*/
#define XLLP_PMU_EVTCOUNT_5					(0x0C02)
/*evtCount0/2:0x7(instruction count), evtCount1/3:0x3(ITLB miss)*/
#define XLLP_PMU_EVTCOUNT_6					(0x0307)
/*evtCount0/2:0xA(DCache Access), evtCount/31:0x4(DTLB miss)*/
#define XLLP_PMU_EVTCOUNT_7					(0x040A)

typedef enum 
{
    PMNC = 0,
    CCNT,
    PMN0,
    PMN1,
	PMN2,
	PMN3,
	INTEN,
	FLAG,
	EVTSEL
}XLLP_PMU_REGNUMBER;

extern unsigned int XllpReadPMUReg(unsigned int aReg);
extern void XllpWritePMUReg(unsigned int aReg, unsigned int aValue);



#endif //__PMU_H__