xllp_ci.c

PXA270硬件测试源代码

        value &= ~XLLP_CI_CICR0_PAR_EN;
    }
    WRITE_REG(XLLP_CICR0, value);   
    return; 
}

void XllpCIConfigureES(unsigned int ci_reg_base, int parity_check)
{
    // the operationi is same as Embedded-Parallel
    XllpCIConfigureEP(ci_reg_base, parity_check);
}

void XllpCISetClock(unsigned int ci_reg_base, unsigned int clk_regs_base, int pclk_enable, int mclk_enable, unsigned int mclk_mhz)
{
    unsigned int ciclk,  value, div, cccr_l;
    P_XLLP_CLKMGR_T pclk;
	float p;

    // determine the LCLK frequency programmed into the CCCR.
    pclk = (P_XLLP_CLKMGR_T)clk_regs_base;
    cccr_l = (pclk->cccr & 0x0000001F);

	if (cccr_l < 8) // L = [2 - 7]
		ciclk = (13 * cccr_l) * 100;
	else if (cccr_l < 17) // L = [8 - 16] 
		ciclk = ((13 * cccr_l) * 100) >> 1;
	else if (cccr_l < 32) // L = [17 - 31]
		ciclk = ((13 * cccr_l) * 100) >> 2;
	
	p = (float)((ciclk / mclk_mhz) - 2) / 2;

	div = (unsigned int) (ceil(p));

    // write cicr4
    value = READ_REG(XLLP_CICR4);
    value &= ~(XLLP_CI_CICR4_PCLK_EN | XLLP_CI_CICR4_MCLK_EN | XLLP_CI_CICR4_DIV_SMASK<<XLLP_CI_CICR4_DIV_SHIFT);
    value |= (pclk_enable) ? XLLP_CI_CICR4_PCLK_EN : 0;
    value |= (mclk_enable) ? XLLP_CI_CICR4_MCLK_EN : 0;
    value |= div << XLLP_CI_CICR4_DIV_SHIFT;
    WRITE_REG(XLLP_CICR4, value);   
    return; 
}

void XllpCISetPolarity(unsigned int ci_reg_base, int pclk_sample_falling, int hsync_active_low, int vsync_active_low)
{
    unsigned int value;

    // write cicr4
    value = READ_REG(XLLP_CICR4);
    value &= ~(XLLP_CI_CICR4_PCP | XLLP_CI_CICR4_HSP | XLLP_CI_CICR4_VSP);
    value |= (pclk_sample_falling)? XLLP_CI_CICR4_PCP : 0;
    value |= (hsync_active_low) ? XLLP_CI_CICR4_HSP : 0;
    value |= (vsync_active_low) ? XLLP_CI_CICR4_VSP : 0;
    WRITE_REG(XLLP_CICR4, value);   
    return; 
}

void XllpCISetFIFO(unsigned int ci_reg_base, unsigned int timeout, XLLP_CI_FIFO_THRESHOLD threshold, int fifo1_enable,
                   int fifo2_enable)
{
    unsigned int value;

    // write citor
    WRITE_REG(XLLP_CITOR, timeout); 
    
    // write cifr: always enable fifo 0! also reset input fifo 
    value = READ_REG(XLLP_CIFR);
    value &= ~(XLLP_CI_CIFR_FEN0 | XLLP_CI_CIFR_FEN1 | XLLP_CI_CIFR_FEN2 | XLLP_CI_CIFR_RESETF | 
                XLLP_CI_CIFR_THL_0_SMASK<<XLLP_CI_CIFR_THL_0_SHIFT);
    value |= (unsigned int)threshold << XLLP_CI_CIFR_THL_0_SHIFT;
    value |= (fifo1_enable) ? XLLP_CI_CIFR_FEN1 : 0;
    value |= (fifo2_enable) ? XLLP_CI_CIFR_FEN2 : 0;
    value |= XLLP_CI_CIFR_RESETF | XLLP_CI_CIFR_FEN0;
    WRITE_REG(XLLP_CIFR, value);    
    return; 
}

void XllpCIResetFIFO(unsigned int ci_reg_base)
{
    unsigned int value;
    value = READ_REG(XLLP_CIFR);
    value |= XLLP_CI_CIFR_RESETF;
    WRITE_REG(XLLP_CIFR, value);    
}

void XllpCISetInterruptMask(unsigned int ci_reg_base, unsigned int mask)
{
    unsigned int value;

    // write mask in cicr0  
    value = READ_REG(XLLP_CICR0);
    value &= ~XLLP_CI_CICR0_INTERRUPT_MASK;
    value |= (mask & XLLP_CI_CICR0_INTERRUPT_MASK);
    WRITE_REG(XLLP_CICR0, value);   
    return; 
}

unsigned int XllpCIGetInterruptMask(unsigned int ci_reg_base)
{
    unsigned int value;

    // write mask in cicr0  
    value = READ_REG(XLLP_CICR0);
    return (value & XLLP_CI_CICR0_INTERRUPT_MASK);
}

void XllpCIClearInterruptStatus(unsigned int ci_reg_base, unsigned int status)
{
    // write 1 to clear
    WRITE_REG(XLLP_CISR, status);
}

unsigned int XllpCIGetInterruptStatus(unsigned int ci_reg_base)
{
    return  READ_REG(XLLP_CISR);
}

void XllpCISetRegisterValue(unsigned int ci_reg_base, unsigned int reg_offset, unsigned int value)
{
	WRITE_REG(reg_offset, value);
}

//-------------------------------------------------------------------------------------------------------
//      Control APIs
//-------------------------------------------------------------------------------------------------------
void XllpCIInit(unsigned int ci_reg_base, unsigned int clk_regs_base)
{
    P_XLLP_CLKMGR_T pclk;
    XLLP_UINT32_T   lock_id;

    // clear all CI registers
    WRITE_REG(XLLP_CICR0, 0x3FF);   // disable all interrupts
    WRITE_REG(XLLP_CICR1, 0);
    WRITE_REG(XLLP_CICR2, 0);
    WRITE_REG(XLLP_CICR3, 0);
    WRITE_REG(XLLP_CICR4, 0);
    WRITE_REG(XLLP_CISR, ~0);
    WRITE_REG(XLLP_CIFR,  0);
    WRITE_REG(XLLP_CITOR, 0);

    // enable CI clock
    lock_id = XllpLock(CKEN);
    pclk = (P_XLLP_CLKMGR_T)clk_regs_base;
    pclk->cken |= XLLP_CLKEN_CAMERA;
    XllpUnlock(lock_id);
}

void XllpCIDeInit(unsigned int ci_reg_base, unsigned int clk_regs_base)
{
    P_XLLP_CLKMGR_T pclk;
    XLLP_UINT32_T   lock_id;
        
    // disable CI clock
    lock_id = XllpLock(CKEN);
    pclk = (P_XLLP_CLKMGR_T)clk_regs_base;
    pclk->cken &= ~XLLP_CLKEN_CAMERA;
    XllpUnlock(lock_id);
}

void XllpCIEnable(unsigned int ci_reg_base, int dma_en)
{
    unsigned int value;

    // write mask in cicr0  
    value = READ_REG(XLLP_CICR0);
    value |= XLLP_CI_CICR0_ENB;
    if (dma_en) {
        value |= XLLP_CI_CICR0_DMA_EN;
    }
    WRITE_REG(XLLP_CICR0, value);   
    return; 
}

void XllpCIDisableComplete(unsigned int ci_reg_base)
{
	unsigned int value;
	
	// Clear the disable control bit.
	value = READ_REG(XLLP_CICR0);
	value &= ~XLLP_CI_CICR0_DIS;
	WRITE_REG( XLLP_CICR0, value );
}

int XllpCIDisable(unsigned int ci_reg_base, unsigned int ost_reg_base, int quick, int wait_for_disable_complete )
{
    volatile unsigned int value, mask;
    int retry;
    
    // write control bit in cicr0   
    value = READ_REG(XLLP_CICR0);
    if (quick) {
        value &= ~XLLP_CI_CICR0_ENB;
        mask = XLLP_CI_CISR_CQD;
    }
    else {
        value |= XLLP_CI_CICR0_DIS;
        mask = XLLP_CI_CISR_CDD;
    }
    WRITE_REG(XLLP_CICR0, value);   

	if( wait_for_disable_complete )
	{
	    // wait shutdown complete
	    retry = 50;
	    while ( retry-- > 0 ) {
	        value = READ_REG(XLLP_CISR);        
	        if ( value & mask ) {
	            WRITE_REG(XLLP_CISR, mask);
	            return 0;
	        }
	        XllpOstDelayMilliSeconds((P_XLLP_OST_T)ost_reg_base, 10);
	    }
	}
	else
		return 0;
	
    return -1; 
}

void XllpCISlaveCaptureEnable(unsigned int ci_reg_base)
{
    unsigned int value;

    // write mask in cicr0  
    value = READ_REG(XLLP_CICR0);
    value |= XLLP_CI_CICR0_SL_CAP_EN;
    WRITE_REG(XLLP_CICR0, value);   
    return; 
}

void XllpCISlaveCaptureDisable(unsigned int ci_reg_base)
{
    unsigned int value;

    // write mask in cicr0  
    value = READ_REG(XLLP_CICR0);
    value &= ~XLLP_CI_CICR0_SL_CAP_EN;
    WRITE_REG(XLLP_CICR0, value);   
    return; 
}