pcnethw.h

winNT技术操作系统,国外开放的原代码和LIUX一样

#define CSR5_MPPLBA    0x20     /* magic packet physical logical broadcast accept */
#define CSR5_EXDINTE   0x40     /* excessive deferral interrupt enable */
#define CSR5_EXDINT    0x80     /* excessive deferral interrupt */
#define CSR5_SLPINTE   0x100    /* sleep interrupt enable */
#define CSR5_SLPINT    0x200    /* sleep interrupt */
#define CSR5_SINE      0x400    /* system interrupt enable */
#define CSR5_SINT      0x800    /* system interrupt */
#define CSR5_LTINTEN   0x4000   /* last transmit interrupt enable */
#define CSR5_TOKINTD   0x8000   /* transmit ok interrupt disable */

/* CSR15 bits */
#define CSR15_DRX      0x1      /* disable receiver */
#define CSR15_DTX      0x2      /* disable transmitter */
#define CSR15_LOOP     0x4      /* loopback enable */
#define CSR15_DXMTFCS  0x8      /* disable transmit fcs */
#define CSR15_FCOLL    0x10     /* force collision */
#define CSR15_DRTY     0x20     /* disable retry */
#define CSR15_INTL     0x40     /* internal loopback */
#define CSR15_PORTSEL0 0x80     /* port selection bit 0 */
#define CSR15_PORTSEL1 0x100    /* port selection bit 1 */
#define CSR15_LRT      0x200    /* low receive threshold - same as TSEL */
#define CSR15_TSEL     0x200    /* transmit mode select - same as LRT */
#define CSR15_MENDECL  0x400    /* mendec loopback mode */
#define CSR15_DAPC     0x800    /* disable automatic parity correction */
#define CSR15_DLNKTST  0x1000   /* disable link status */
#define CSR15_DRCVPA   0x2000   /* disable receive physical address */
#define CSR15_DRCVBC   0x4000   /* disable receive broadcast */
#define CSR15_PROM     0x8000   /* promiscuous mode */

/* CSR58 bits */
#define CSR58_SSIZE32  0x100    /* 32-bit software size */
#define CSR58_CSRPCNET 0x200    /* csr pcnet-isa configuration */
#define CSR58_APERREN  0x400    /* advanced parity error handling enable */

/* CSR124 bits */
#define CSR124_RPA     0x4      /* runt packet accept */

/* BCR2 bits */
#define BCR2_ASEL      0x2      /* auto-select media */
#define BCR2_AWAKE     0x4      /* select sleep mode */
#define BCR2_EADISEL   0x8      /* eadi select */
#define BCR2_DXCVRPOL  0x10     /* dxcvr polarity */
#define BCR2_DXCVRCTL  0x20     /* dxcvr control */
#define BCR2_INTLEVEL  0x80     /* interrupt level/edge */
#define BCR2_APROMWE   0x100    /* address prom write enable */
#define BCR2_TMAULOOP  0x4000   /* t-mau transmit on loopback */

/* BCR4 bits */
#define BCR4_COLE      0x1      /* collision status enable */
#define BCR4_JABE      0x2      /* jabber status enable */
#define BCR4_RCVE      0x4      /* receive status enable */
#define BCR4_RXPOLE    0x8      /* receive polarity status enable */
#define BCR4_XMTE      0x10     /* transmit status enable */
#define BCR4_RCVME     0x20     /* receive match status enable */
#define BCR4_LNKSTE    0x40     /* link status enable */
#define BCR4_PSE       0x80     /* pulse stretcher enable */
#define BCR4_FDLSE     0x100    /* full-duplex link status enable */
#define BCR4_MPSE      0x200    /* magic packet status enable */
#define BCR4_LEDDIS    0x2000   /* led disable */
#define BCR4_LEDPOL    0x4000   /* led polarity */
#define BCR4_LEDOUT    0x8000   /* led output pin value */

/* BCR5 bits */
#define BCR5_COLE      0x1      /* collision status enable */
#define BCR5_JABE      0x2      /* jabber status enable */
#define BCR5_RCVE      0x4      /* receive status enable */
#define BCR5_RXPOLE    0x8      /* receive polarity status enable */
#define BCR5_XMTE      0x10     /* transmit status enable */
#define BCR5_RCVME     0x20     /* receive match status enable */
#define BCR5_LNKSTE    0x40     /* link status enable */
#define BCR5_PSE       0x80     /* pulse stretcher enable */
#define BCR5_FDLSE     0x100    /* full-duplex link status enable */
#define BCR5_MPSE      0x200    /* magic packet status enable */
#define BCR5_LEDDIS    0x2000   /* led disable */
#define BCR5_LEDPOL    0x4000   /* led polarity */
#define BCR5_LEDOUT    0x8000   /* led output pin value */

/* BCR6 bits */
#define BCR6_COLE      0x1      /* collision status enable */
#define BCR6_JABE      0x2      /* jabber status enable */
#define BCR6_RCVE      0x4      /* receive status enable */
#define BCR6_RXPOLE    0x8      /* receive polarity status enable */
#define BCR6_XMTE      0x10     /* transmit status enable */
#define BCR6_RCVME     0x20     /* receive match status enable */
#define BCR6_LNKSTE    0x40     /* link status enable */
#define BCR6_PSE       0x80     /* pulse stretcher enable */
#define BCR6_FDLSE     0x100    /* full-duplex link status enable */
#define BCR6_MPSE      0x200    /* magic packet status enable */
#define BCR6_LEDDIS    0x2000   /* led disable */
#define BCR6_LEDPOL    0x4000   /* led polarity */
#define BCR6_LEDOUT    0x8000   /* led output pin value */

/* BCR7 bits */
#define BCR7_COLE      0x1      /* collision status enable */
#define BCR7_JABE      0x2      /* jabber status enable */
#define BCR7_RCVE      0x4      /* receive status enable */
#define BCR7_RXPOLE    0x8      /* receive polarity status enable */
#define BCR7_XMTE      0x10     /* transmit status enable */
#define BCR7_RCVME     0x20     /* receive match status enable */
#define BCR7_LNKSTE    0x40     /* link status enable */
#define BCR7_PSE       0x80     /* pulse stretcher enable */
#define BCR7_FDLSE     0x100    /* full-duplex link status enable */
#define BCR7_MPSE      0x200    /* magic packet status enable */
#define BCR7_LEDDIS    0x2000   /* led disable */
#define BCR7_LEDPOL    0x4000   /* led polarity */
#define BCR7_LEDOUT    0x8000   /* led output pin value */

/* BCR9 bits */
#define BCR9_FDEN      0x1      /* full-duplex enable */
#define BCR9_AUIFD     0x2      /* aui full-duplex */
#define BCR9_FDRPAD    0x4      /* full-duplex runt packet accept disable */

/* BCR18 bits */
#define BCR18_BWRITE   0x20     /* burst write enable */
#define BCR18_BREADE   0x40     /* burst read enable */
#define BCR18_DWIO     0x80     /* dword i/o enable */
#define BCR18_EXTREQ   0x100    /* extended request */
#define BCR18_MEMCMD   0x200    /* memory command */

/* BCR19 bits */
#define BCR19_EDI      0x1      /* eeprom data in - same as EDO */
#define BCR19_ED0      0x1      /* eeprom data out - same as EDI */
#define BCR19_ESK      0x2      /* eeprom serial clock */
#define BCR19_ECS      0x4      /* eeprom chip select */
#define BCR19_EEN      0x8      /* eeprom port enable */
#define BCR19_EEDET    0x2000   /* eeprom detect */
#define BCR19_PREAD    0x4000   /* eeprom read */
#define BCR19_PVALID   0x8000   /* eeprom valid */

/* BCR20 bits */
#define BCR20_SSIZE32  0x100    /* 32-bit software size */
#define BCR20_CSRPCNET 0x200    /* csr pcnet-isa configuration */
#define BCR20_APERREN  0x400    /* advanced parity error handling enable */

/* initialization block for 32-bit software style */
typedef struct _INITIALIZATION_BLOCK
{
  USHORT MODE;          /* card mode (csr15) */
  UCHAR  RLEN;          /* encoded number of receive descriptor ring entries */
  UCHAR  TLEN;          /* encoded number of transmit descriptor ring entries */
  UCHAR  PADR[6];       /* physical address */
  USHORT RES;           /* reserved */
  UCHAR  LADR[8];       /* logical address */
  ULONG  RDRA;          /* receive descriptor ring address */
  ULONG  TDRA;          /* transmit descriptor ring address */
} INITIALIZATION_BLOCK, *PINITIALIZATION_BLOCK;

/* receive descriptor, software stle 2 (32-bit) */
typedef struct _RECEIVE_DESCRIPTOR
{
  ULONG  RBADR;         /* receive buffer address */
  USHORT BCNT;          /* two's compliment buffer byte count - NOTE: always OR with 0xf000 */
  USHORT FLAGS;         /* flags - always and with 0xfff0 */
  USHORT MCNT;          /* message byte count ; always AND with 0x0fff */
  UCHAR  RPC;           /* runt packet count */
  UCHAR  RCC;           /* receive collision count */
  ULONG  RES;           /* resereved */
} RECEIVE_DESCRIPTOR, *PRECEIVE_DESCRIPTOR;

/* receive descriptor flags */
#define RD_BAM         0x10     /* broadcast address match */
#define RD_LAFM        0x20     /* logical address filter match */
#define RD_PAM         0x40     /* physical address match */
#define RD_BPE         0x80     /* bus parity error */
#define RD_ENP         0x100    /* end of packet */
#define RD_STP         0x200    /* start of packet */
#define RD_BUFF        0x400    /* buffer error */
#define RD_CRC         0x800    /* crc error */
#define RD_OFLO        0x1000   /* overflow error */
#define RD_FRAM        0x2000   /* framing error */
#define RD_ERR         0x4000   /* an error bit is set */
#define RD_OWN         0x8000   /* buffer ownership (0=host, 1=nic) */

/* transmit descriptor, software style 2 */
typedef struct _TRANSMIT_DESCRIPTOR
{
  ULONG  TBADR;         /* transmit buffer address */
  USHORT BCNT;          /* two's compliment buffer byte count - OR with 0xf000 */
  USHORT FLAGS;         /* flags */
  USHORT TRC;           /* transmit retry count (AND with 0x000f */
  USHORT FLAGS2;        /* more flags */
  ULONG  RES;           /* reserved */
} TRANSMIT_DESCRIPTOR, *PTRANSMIT_DESCRIPTOR;

/* transmit descriptor flags */
#define TD1_BPE         0x80    /* bus parity error */
#define TD1_ENP         0x100   /* end of packet */
#define TD1_STP         0x200   /* start of packet */
#define TD1_DEF         0x400   /* frame transmission deferred */
#define TD1_ONE         0x800   /* exactly one retry was needed for transmission */
#define TD1_MORE        0x1000  /* more than 1 transmission retry required - same as LTINT */
#define TD1_LTINT       0x1000  /* suppress transmit success interrupt - same as MORE */
#define TD1_ADD_FCS     0x2000  /* force fcs generation - same as NO_FCS */
#define TD1_NO_FCS      0x2000  /* prevent fcs generation - same as ADD_FCS */
#define TD1_ERR         0x4000  /* an error bit is set */
#define TD1_OWN         0x8000  /* buffer ownership */

/* transmit descriptor flags2 flags */
#define TD2_RTRY        0x400   /* retry error */
#define TD2_LCAR        0x800   /* loss of carrier */
#define TD2_LCOL        0x1000  /* late collision */
#define TD2_EXDEF       0x2000  /* excessive deferral */
#define TD2_UFLO        0x4000  /* buffer underflow */
#define TD2_BUFF        0x8000  /* buffer error */

#endif /* _PCNETHW_ */