dpx_api.c

交换机中常用芯片链路复用7350的驱动源代码(vxworks中实现)

                                                                  u1TestValue);
            sysDuplexRawWrite(pBaseAddr + DPX_REG_INPUT_CELL_AV_EN_MSB, 
                                                                  u1TestValue);
            sysDuplexRawWrite(pBaseAddr + DPX_REG_PHY_OUTPUT_POLL_RANGE, 
                                                           u1TestValue & 0x1F);
        }
        else
        {     /* indirect channnel access */
              sysDuplexRawWrite(pBaseAddr + DPX_REG_RCV_SER_IND_CHNL_SELECT,
                                                           u1TestValue & 0x6F);
              sysDuplexRawWrite(pBaseAddr + DPX_REG_TX_SER_IND_CHNL_SELECT,
                                                           u1TestValue & 0x4F);                                                         
        }

        sysDuplexRawWrite(pBaseAddr + DPX_REG_RXD1_BOC_RCV_EN, u1TestValue
                                                                       & 0x07);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_TXD1_BOC, u1TestValue & 0x3F);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_TXD2_BOC, u1TestValue & 0x3F);

        sysDuplexRawWrite(pBaseAddr + DPX_REG_MICRO_CELL_BUFF_INT, u1TestValue
                                                                       & 0x0F);

        /* in order to write a value to INSERT_CRC_Accumulator registers, the
           INSCRCPR bit of Reg 21 should be cleared first */ 
        duplexClearRegBits(psDpxDdb->u4BaseAddr, DPX_REG_MICRO_INSERT_FIFO_CTL,
                           DPX_MASK_MICRO_INSERT_FIFO_CTL_INSCRCPR);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_INSERT_CRC_ACC_LSB,u1TestValue);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_INSERT_CRC_ACC_2ND,u1TestValue);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_INSERT_CRC_ACC_3RD,u1TestValue);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_INSERT_CRC_ACC_MSB,u1TestValue);
        
         /* in order to write a value to EXTRACT_CRC_Accumulator registers, the
           EXTCRCPR bit of Reg 22 should be cleared first */
        duplexClearRegBits(psDpxDdb->u4BaseAddr, DPX_REG_MICRO_EXTRACT_FIFO_CTL,
                           DPX_MASK_MICRO_EXTRACT_FIFO_EXTCRCPR);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_EXTRACT_CRC_ACC_LSB,u1TestValue);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_EXTRACT_CRC_ACC_2ND,u1TestValue);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_EXTRACT_CRC_ACC_3RD,u1TestValue);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_EXTRACT_CRC_ACC_MSB,u1TestValue);

       /* DPX_REG_MICRO_CELL_BUFF_DATA register is not tested here */ 
                                                                   
        sysDuplexRawWrite(pBaseAddr + DPX_REG_RXD1_EFIFO_CTL, u1TestValue 
                                                                        & 0x03);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_RXD2_EFIFO_CTL, u1TestValue 
                                                                        & 0x03);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_RCV_LC_FIFO_CTL, u1TestValue 
                                                                        & 0x03);

        sysDuplexRawWrite(pBaseAddr + DPX_REG_RXD1_HSS_CFG, u1TestValue 
                                                                        & 0xDF);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_RXD2_HSS_CFG, u1TestValue 
                                                                        & 0xDF);

        sysDuplexRawWrite(pBaseAddr + DPX_REG_RXD1_HSS_INT_EN, u1TestValue
                                                                        & 0x7F);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_RXD2_HSS_INT_EN, u1TestValue 
                                                                        & 0x7F);

        sysDuplexRawWrite(pBaseAddr + DPX_REG_TX_LC_FIFO_CTL, u1TestValue 
                                                                        & 0x03);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_TX_LC_FIFO_DEPTH, u1TestValue 
                                                                        & 0x3F);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_TX_LC_FIFO_READY, u1TestValue 
                                                                        & 0x3F);
        sysDuplexRawWrite(pBaseAddr + DPX_REG_TX_HSS_CFG, u1TestValue &0xDF);

       
        /* read back */
        sysDuplexRawRead(pBaseAddr + DPX_REG_MASTER_CFG, u1TestValue);
        if(u1TestValue != DPX_REGISTER_TEST_VALUE)
        {
#if DPX_DEBUG_MSG_ON
             printf("dpxRegisterTest: DPX_REG_MASTER_CFG, 0x%x\n", u1TestValue);
#endif
             return DPX_ERR_FAILURE;
        }

        sysDuplexRawRead(pBaseAddr + DPX_REG_SER_LNK_MNT, u1TestValue);
        if(u1TestValue != DPX_REGISTER_TEST_VALUE)
        {
#if DPX_DEBUG_MSG_ON
             printf("dpxRegisterTest: DPX_REG_SER_LNK_MNT, 0x%x\n", u1TestValue);
#endif             
             return DPX_ERR_FAILURE;
        }

        if(eDpxMode != DPX_CLK_BIT_SER)
        {
            /* PHY interface */
            sysDuplexRawRead(pBaseAddr + DPX_REG_EXT_ADDR_MATCH_LSB, u1TestValue);
            if(u1TestValue != DPX_REGISTER_TEST_VALUE)
            {
#if DPX_DEBUG_MSG_ON
                printf("dpxRegisterTest: DPX_REG_EXT_ADDR_MATCH_LSB, 0x%x\n", u1TestValue);
#endif
                return DPX_ERR_FAILURE;
            }


	        sysDuplexRawRead(pBaseAddr + DPX_REG_EXT_ADDR_MATCH_MSB, u1TestValue);
            if((u1TestValue&0x07) != (DPX_REGISTER_TEST_VALUE&0x07))
            {
#if DPX_DEBUG_MSG_ON            
                printf("dpxRegisterTest: DPX_REG_EXT_ADDR_MATCH_MSB, 0x%x\n", u1TestValue);
#endif
                return DPX_ERR_FAILURE;
            }


      	    sysDuplexRawRead(pBaseAddr + DPX_REG_EXT_ADDR_MASK_LSB, u1TestValue);
            if(u1TestValue != DPX_REGISTER_TEST_VALUE)
            {
#if DPX_DEBUG_MSG_ON
                printf("dpxRegisterTest: DPX_REG_EXT_ADDR_MASK_LSB, 0x%x\n", u1TestValue);
#endif 
                return DPX_ERR_FAILURE;
            }

	        sysDuplexRawRead(pBaseAddr + DPX_REG_EXT_ADDR_MASK_MSB, u1TestValue);
            if((u1TestValue&0x07) != (DPX_REGISTER_TEST_VALUE&0x07))
            {
#if DPX_DEBUG_MSG_ON            
                printf("dpxRegisterTest: DPX_REG_EXT_ADDR_MASK_MSB, 0x%x\n", u1TestValue);
#endif
                return DPX_ERR_FAILURE;
            }

	        sysDuplexRawRead(pBaseAddr + DPX_REG_OUTPUT_ADDR_MATCH, u1TestValue);
            if((u1TestValue&0x3F) != (DPX_REGISTER_TEST_VALUE&0x3F))
            {
#if DPX_DEBUG_MSG_ON            
                printf("dpxRegisterTest: DPX_REG_OUTPUT_ADDR_MATCH, 0x%x\n", u1TestValue);
#endif
                return DPX_ERR_FAILURE;
            }

	        sysDuplexRawRead(pBaseAddr + DPX_REG_PHY_INPUT_CFG2, u1TestValue);
            if((u1TestValue&0x7F) != (DPX_REGISTER_TEST_VALUE&0x7F))
            {
#if DPX_DEBUG_MSG_ON            
                printf("dpxRegisterTest:  DPX_REG_PHY_INPUT_CFG2, 0x%x\n", u1TestValue);
#endif
                return DPX_ERR_FAILURE;
            }


            sysDuplexRawRead(pBaseAddr + DPX_REG_INPUT_CELL_AV_EN_LSB,u1TestValue);
            if(u1TestValue != DPX_REGISTER_TEST_VALUE)
            {
#if DPX_DEBUG_MSG_ON            
                printf("dpxRegisterTest: DPX_REG_INPUT_CELL_AV_EN_LSB, 0x%x\n", u1TestValue);
#endif
                return DPX_ERR_FAILURE;
            }

	        sysDuplexRawRead(pBaseAddr + DPX_REG_INPUT_CELL_AV_EN_2ND,u1TestValue);
            if(u1TestValue != DPX_REGISTER_TEST_VALUE)
            {
#if DPX_DEBUG_MSG_ON           
                printf("dpxRegisterTest: DPX_REG_INPUT_CELL_AV_EN_2ND, 0x%x\n", u1TestValue);
#endif
                return DPX_ERR_FAILURE;
            }

	        sysDuplexRawRead(pBaseAddr + DPX_REG_INPUT_CELL_AV_EN_3RD,u1TestValue);
            if(u1TestValue != DPX_REGISTER_TEST_VALUE)
            {
#if DPX_DEBUG_MSG_ON            
                printf("dpxRegisterTest: DPX_REG_INPUT_CELL_AV_EN_3RD, 0x%x\n", u1TestValue);
#endif
                return DPX_ERR_FAILURE;
            }


	        sysDuplexRawRead(pBaseAddr + DPX_REG_INPUT_CELL_AV_EN_MSB,u1TestValue);
            if(u1TestValue != DPX_REGISTER_TEST_VALUE)
            {
#if DPX_DEBUG_MSG_ON            
                printf("dpxRegisterTest: DPX_REG_INPUT_CELL_AV_EN_MSB, 0x%x\n", u1TestValue);
#endif
                return DPX_ERR_FAILURE;
            }


	        sysDuplexRawRead(pBaseAddr + DPX_REG_PHY_OUTPUT_POLL_RANGE,u1TestValue);
            if((u1TestValue&0x1F) != (DPX_REGISTER_TEST_VALUE&0x1F))
            {
#if DPX_DEBUG_MSG_ON            
                printf("dpxRegisterTest: DPX_REG_PHY_OUTPUT_POLL_RANGE, 0x%x\n", u1TestValue);
#endif
                return DPX_ERR_FAILURE;
            }
       }
       else
       {
            /* indirect channnel access */
              sysDuplexRawRead(pBaseAddr + DPX_REG_RCV_SER_IND_CHNL_SELECT, u1TestValue);
              if((u1TestValue & 0x6F) != (DPX_REGISTER_TEST_VALUE & 0x6F))
              {
#if DPX_DEBUG_MSG_ON              
                printf("dpxRegisterTest: DPX_REG_RCV_SER_IND_CHNL_SELECT, 0x%x\n", u1TestValue);
#endif
                return DPX_ERR_FAILURE;
              }


              sysDuplexRawRead(pBaseAddr + DPX_REG_TX_SER_IND_CHNL_SELECT, u1TestValue);
              if((u1TestValue & 0x4F) != (DPX_REGISTER_TEST_VALUE&0x4F))
              {
#if DPX_DEBUG_MSG_ON              
                printf("dpxRegisterTest: DPX_REG_TX_SER_IND_CHNL_SELECT, 0x%x\n", u1TestValue);
#endif
                return DPX_ERR_FAILURE;
              }                 
       
       }
       
	   sysDuplexRawRead(pBaseAddr + DPX_REG_RXD1_BOC_RCV_EN,u1TestValue);
       if((u1TestValue&0x07) != (DPX_REGISTER_TEST_VALUE&0x07))
        {
#if DPX_DEBUG_MSG_ON        
             printf("dpxRegisterTest: DPX_REG_RXD1_BOC_RCV_EN, 0x%x\n", u1TestValue);
#endif
             return DPX_ERR_FAILURE;
        }

	   sysDuplexRawRead(pBaseAddr + DPX_REG_TXD1_BOC, u1TestValue);
       if((u1TestValue&0x3F) != (DPX_REGISTER_TEST_VALUE&0x3F))
        {
#if DPX_DEBUG_MSG_ON        
             printf("dpxRegisterTest: DPX_REG_TXD1_BOC, 0x%x\n", u1TestValue);
#endif
             return DPX_ERR_FAILURE;
        }

	    sysDuplexRawRead(pBaseAddr + DPX_REG_TXD2_BOC, u1TestValue);
        if((u1TestValue&0x3F) != (DPX_REGISTER_TEST_VALUE&0x3F))
        {
#if DPX_DEBUG_MSG_ON        
             printf("dpxRegisterTest: DPX_REG_TXD2_BOC, 0x%x\n", u1TestValue);
#endif
             return DPX_ERR_FAILURE;
        }


        sysDuplexRawRead(pBaseAddr + DPX_REG_MICRO_CELL_BUFF_INT, u1TestValue);
        if((u1TestValue&0x0F) != (DPX_REGISTER_TEST_VALUE&0x0F))
        {
#if DPX_DEBUG_MSG_ON        
             printf("dpxRegisterTest: DPX_REG_MICRO_CELL_BUFF_INT, 0x%x\n", u1TestValue);
#endif
             return DPX_ERR_FAILURE;
        }

        sysDuplexRawRead(pBaseAddr + DPX_REG_INSERT_CRC_ACC_LSB, u1TestValue);
        if(u1TestValue != DPX_REGISTER_TEST_VALUE)
        {
#if DPX_DEBUG_MSG_ON        
             printf("dpxRegisterTest: DPX_REG_INSERT_CRC_ACC_LSB, 0x%x\n", u1TestValue);
#endif
             return DPX_ERR_FAILURE;
        }

     	sysDuplexRawRead(pBaseAddr + DPX_REG_INSERT_CRC_ACC_2ND, u1TestValue);
        if(u1TestValue != DPX_REGISTER_TEST_VALUE)
        {
#if DPX_DEBUG_MSG_ON       
             printf("dpxRegisterTest: DPX_REG_INSERT_CRC_ACC_2ND, 0x%x\n", u1TestValue);
#endif 
             return DPX_ERR_FAILURE;
        }

    	sysDuplexRawRead(pBaseAddr + DPX_REG_INSERT_CRC_ACC_3RD, u1TestValue);
        if(u1TestValue != DPX_REGISTER_TEST_VALUE)
        {
#if DPX_DEBUG_MSG_ON        
             printf("dpxRegisterTest: DPX_REG_INSERT_CRC_ACC_3RD, 0x%x\n", u1TestValue);
#endif
             return DPX_ERR_FAILURE;
        }

    	sysDuplexRawRead(pBaseAddr + DPX_REG_INSERT_CRC_ACC_MSB, u1TestValue);
        if(u1TestValue != DPX_REGISTER_TEST_VALUE)
        {
#if DPX_DEBUG_MSG_ON        
             printf("dpxRegisterTest: DPX_REG_INSERT_CRC_ACC_MSB, 0x%x\n", u1TestValue);
#endif
             return DPX_ERR_FAILURE;
        }


    	sysDuplexRawRead(pBaseAddr + DPX_REG_EXTRACT_CRC_ACC_LSB, u1TestValue);
        if(u1TestValue != DPX_REGISTER_TEST_VALUE)
        {
#if DPX_DEBUG_MSG_ON        
             printf("dpxRegisterTest: DPX_REG_EXTRACT_CRC_ACC_LSB, 0x%x\n", u1TestValue);
#endif
             return DPX_ERR_FAILURE;
        }

	    sysDuplexRawRead(pBaseAddr + DPX_REG_EXTRACT_CRC_ACC_2ND, u1TestValue);
        if(u1TestValue != DPX_REGISTER_TEST_VALUE)
        {
#if DPX_DEBUG_MSG_ON        
             printf("dpxRegisterTest: DPX_REG_EXTRACT_CRC_ACC_2ND, 0x%x\n", u1TestValue);
#endif
             return DPX_ERR_FAILURE;
        }


	    sysDuplexRawRead(pBaseAddr + DPX_REG_EXTRACT_CRC_ACC_3RD, u1TestValue);
        if(u1TestValue != DPX_REGISTER_TEST_VALUE)
        {
#if DPX_DEBUG_MSG_ON        
             printf("dpxRegisterTest: DPX_REG_EXTRACT_CRC_ACC_3RD, 0x%x\n", u1TestValue);
#endif
             return DPX_ERR_FAILURE;
        }

	    sysDuplexRawRead(pBaseAddr + DPX_REG_EXTRACT_CRC_ACC_MSB, u1TestValue);
        if(u1TestValue != DPX_REGISTER_TEST_VALUE)
        {
 #if DPX_DEBUG_MSG_ON       
             printf("dpxRegisterTest: DPX_REG_EXTRACT_CRC_ACC_MSB, 0x%x\n", u1TestValue);
 #endif
             return DPX_ERR_FAILURE;
        }

       /* DPX_REG_MICRO_CELL_BUFF_DATA register is not tested here */

        sysDuplexRawRead(pBaseAddr + DPX_REG_RXD1_EFIFO_CTL,u1TestValue);
        if((u1TestValue&0x03) != (DPX_REGISTER_TEST_VALUE&0x03))
        {
 #if DPX_DEBUG_MSG_ON       
             printf("dpxRegisterTest: DPX_REG_RXD1_EFIFO_CTL, 0x%x\n", u1TestValue);
 #endif
             return DPX_ERR_FAILURE;
        }


    	sysDuplexRawRead(pBaseAddr + DPX_REG_RXD2_EFIFO_CTL, u1TestValue);
        if((u1TestValue&0x03) != (DPX_REGISTER_TEST_VALUE&0x03))
        {
 #if DPX_DEBUG_MSG_ON
             printf("dpxRegisterTest: DPX_REG_RXD2_EFIFO_CTL, 0x%x\n", u1TestValue);
 #endif
             return DPX_ERR_FAILURE;
        }


    	sysDuplexRawRead(pBaseAddr + DPX_REG_RCV_LC_FIFO_CTL, u1TestValue);
        if((u1TestValue&0x03) != (DPX_REGISTER_TEST_VALUE&0x03))
        {
#if DPX_DEBUG_MSG_ON        
             printf("dpxRegisterTest: DPX_REG_RCV_LC_FIFO_CTL, 0x%x\n", u1TestValue);
#endif
             return DPX_ERR_FAILURE;
        }