dpx.c

交换机中常用芯片链路复用7350的驱动源代码(vxworks中实现)

**  dpxTxIndChnlWrite
**  ___________________________________________________________________________ 
**
**  DESCRIPTION:   Write a value into Trasmit Indirect Channel registers.  
**                 For driver internal use only
**
**  VALID STATES:  Not applicable
**
**  SIDE EFFECTS:  None.
**
**  INPUTS:		   u4BaseAddr - base address of the DUPLEX device
**                 u1RegID - address offset for Rx Indirect Channel registers
**                 u1ChannelID - channel number
**                 u1Value - the value to be written
**
**  OUTPUTS:	   None
**
**  RETURN CODES:  DPX_SUCCESS
**                 DPX_ERR_INDIRECT_CHANNEL_BUSY (timeout for indirect channel
**                                                access)  
**
*******************************************************************************/
  
INT4 dpxTxIndChnlWrite(UINT4 u4BaseAddr, UINT1 u1RegID, UINT1 u1ChannelID, 
                                                                  UINT1 u1Value) 
{
    UINT1 u1Select=0;
    UINT4 i = 0;

	/* check and wait for the Indirect Access Busy bit to be cleared */
	do 
	{
	   sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_TX_SER_IND_CHNL_SELECT), 
	                       u1Select);
	   i++;
       if(i > DPX_IND_CHNL_TIMEOUT)
            return(DPX_ERR_INDIRECT_CHANNEL_BUSY);
	
    }
	while (u1Select & DPX_MASK_IND_CHNL_SELECT_CBUSY);
	
 	/* write the content into Tx Clocked Serial Registers */
    sysDuplexRawWrite((INT1 *)(u4BaseAddr + u1RegID), u1Value);

    /* select the channel and clear CRWB bit to trigger a write operation */
    u1Select = (u1ChannelID & ~DPX_MASK_IND_CHNL_SELECT_CRWB); 
    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_TX_SER_IND_CHNL_SELECT), 
                                                                      u1Select);

	/* wait for the write operation to be completed */
	i = 0;
    do 
	{
	   sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_TX_SER_IND_CHNL_SELECT), 
	                       u1Select);
	   i++;
       if(i > DPX_IND_CHNL_TIMEOUT)
            return(DPX_ERR_INDIRECT_CHANNEL_BUSY);
	
    }
	while (u1Select & DPX_MASK_IND_CHNL_SELECT_CBUSY);
    
    return(DPX_SUCCESS);

}

/*******************************************************************************
**
**  dpxTxIndChnlRead
**  ___________________________________________________________________________ 
**
**  DESCRIPTION:   Read a value from a Transmit Indirect Channel register.  
**                 For driver internal use only
**
**  VALID STATES:  Not applicable
**
**  SIDE EFFECTS:  None.
**
**  INPUTS:		   u4BaseAddr - base address of the DUPLEX device
**                 u1RegID - address offset for Rx Indirect Channel register
**                 u1ChannelID - channel number
**
**  OUTPUTS:	   pu1Value - pointer to the value read
**
**  RETURN CODES:  DPX_SUCCESS
**                 DPX_ERR_INDIRECT_CHANNEL_BUSY (timeout for indirect channel
**                                                access) 
**
*******************************************************************************/
INT4 dpxTxIndChnlRead(UINT4 u4BaseAddr, UINT1 RegID, UINT1 ChannelID, 
                                                               UINT1 *pu1Value) 
{
    UINT1 u1Select = 0;
    UINT4 i = 0;
    
	/*  wait for interface to be available i.e. the Indirect Access Busy bit 
	    should be cleared */
	do 
	{
	   sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_TX_SER_IND_CHNL_SELECT), 
	                       u1Select);
	   i++;
       if(i > DPX_IND_CHNL_TIMEOUT)
            return(DPX_ERR_INDIRECT_CHANNEL_BUSY);
	
    }
	while (u1Select & DPX_MASK_IND_CHNL_SELECT_CBUSY);

	
    /* select the channel and set CRWB bit to trigger a read operation */
	u1Select = (ChannelID | DPX_MASK_IND_CHNL_SELECT_CRWB); 
    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_TX_SER_IND_CHNL_SELECT), 
                                                                      u1Select);

	/*  wait for the Indirect Access Busy bit to be cleared */
        i = 0;
	do 
	{
	   sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_TX_SER_IND_CHNL_SELECT), 
	                       u1Select);
	   i++;
       if(i > DPX_IND_CHNL_TIMEOUT)
            return(DPX_ERR_INDIRECT_CHANNEL_BUSY);
	
    }
	while (u1Select & DPX_MASK_IND_CHNL_SELECT_CBUSY);

    /* Ok, read the value now */
	sysDuplexRawRead((INT1 *)(u4BaseAddr + RegID), *pu1Value);

    return(DPX_SUCCESS);
}


/*******************************************************************************
**
**  duplexValidateIV
**  ___________________________________________________________________________ 
**
**  DESCRIPTION:  Validate the initialization vector passed in.  
**                For driver internal use only
**
**  VALID STATES:  Not applicable
**
**  SIDE EFFECTS:  None.
**
**  INPUTS:		   eDpxMode - Duplex device mode, 
**                            either DPX_CLK_BIT_SER  or DPX_SCI_MASTER
**                                   or DPX_SCI_ANY_SLAVE
**                 psInitVector - pointer to initialization vector
**
**  OUTPUTS:	   None
**
**  RETURN CODES: 
**                 DPX_SUCCESS  
**                 DPX_ERR_INVALID_INIT_VECTOR     
**
*******************************************************************************/
INT4 duplexValidateIV(eDPX_MODE eDpxMode, sDPX_INIT_VECTOR *psInitVector) 
{
     sDPX_SCI_ANY_PHY_REGS  *psDpxSciAnyPhyRegs;
     sDPX_HSS_REGS          *psDpxHssRegs;

    INT4 ErrorCode = DPX_ERR_INVALID_INIT_VECTOR; 
                        /* assume error, unless approve otherwise ! */

     psDpxSciAnyPhyRegs = 
            (sDPX_SCI_ANY_PHY_REGS  *)&(psInitVector->sRegInfo.sSciAnyPhyRegs);
     psDpxHssRegs = ( sDPX_HSS_REGS *) & (psInitVector->sRegInfo.sHssRegs);

     if(eDpxMode != DPX_CLK_BIT_SER)
     {
        /** THIS PHY mode, we need validate the Phy related Initial Vector */
        /* check Parity Type consistence between Input/Output SCI-PHY/ANY-PHY */
        if((psDpxSciAnyPhyRegs->u1SciAnyPhyInpCfg[0]
            & DPX_MASK_PHY_INPUT_CFG1_PTYP) !=
            (psDpxSciAnyPhyRegs->u1SciAnyPhyOutCfg & 
            DPX_MASK_PHY_OUTPUT_CFG_PTYP))
          return (ErrorCode);

        /* check Prepend consistence between Input/Output SCI-PHY/ANY-PHY */
        if(((psDpxSciAnyPhyRegs->u1SciAnyPhyInpCfg[0] & 
            DPX_MASK_PHY_INPUT_CFG1_PRELEN)>>2) !=
            (psDpxSciAnyPhyRegs->u1SciAnyPhyOutCfg & 
            DPX_MASK_PHY_OUTPUT_CFG_PRELEN)>>1)
          return (ErrorCode);

        /* check H5UDF bit consistence between Input/Output SCI-PHY/ANY-PHY */
        if(((psDpxSciAnyPhyRegs->u1SciAnyPhyInpCfg[0] & 
            DPX_MASK_PHY_INPUT_CFG1_H5UDF)>>4) !=
            (psDpxSciAnyPhyRegs->u1SciAnyPhyOutCfg & 
            DPX_MASK_PHY_OUTPUT_CFG_H5UDF))
          return (ErrorCode);
         
        /* PHY device polling range between Input/Output SCI-PHY/ANY-PHY when it's
            a bus master */
        if((psDpxSciAnyPhyRegs->u1SciAnyPhyInpCfg[1] & 
            DPX_MASK_PHY_INPUT_CFG2_PHYDEV) !=
            (psDpxSciAnyPhyRegs->u1SciAnyPhyOutPollRng & 
            DPX_MASK_PHY_OUTPUT_POLLING_PHYDEV))
          return (ErrorCode);
      }

      /* Check HSS Configuration */
       /** RXD1 == RXD2 Configuration */
       if(psDpxHssRegs->u1RxCfg[0]  != psDpxHssRegs->u1RxCfg[1] )
            return (ErrorCode);

      /*** length of user header between TX and RX ***/
      if((psDpxHssRegs->u1RxCfg[0] & DPX_MASK_HSS_RX_CFG_USRHDR) !=
            (psDpxHssRegs->u1TxCfg & DPX_MASK_HSS_TX_CFG_USRHDR))
          return (ErrorCode);

      /*** Prepend ***/
      if((psDpxHssRegs->u1RxCfg[0] & DPX_MASK_HSS_RX_CFG_PREPEND) !=
            (psDpxHssRegs->u1TxCfg & DPX_MASK_HSS_TX_CFG_PREPEND))
          return (ErrorCode);

      /*** CRC-8 protection ***/
      if((psDpxHssRegs->u1RxCfg[0] & DPX_MASK_HSS_RX_CFG_CELLCRC) !=
            (psDpxHssRegs->u1TxCfg & DPX_MASK_HSS_TX_CFG_CELLCRC))
          return (ErrorCode);

      /*** RX Descramble and TX Scramble **/
     if((psDpxHssRegs->u1RxCfg[0] & DPX_MASK_HSS_RX_CFG_DDSCR) !=
            (psDpxHssRegs->u1TxCfg & DPX_MASK_HSS_TX_CFG_DSCR))
          return (ErrorCode);

     if((psDpxHssRegs->u1RxCfg[0] & DPX_MASK_HSS_RX_CFG_HDSCR) !=
           ( psDpxHssRegs->u1TxCfg & DPX_MASK_HSS_TX_CFG_HSCR))
          return (ErrorCode);

  
	ErrorCode = DPX_SUCCESS;
	return (ErrorCode); 

}

/*******************************************************************************
**
**  duplexHWCfgReg
**  ___________________________________________________________________________ 
**
**  DESCRIPTION:   Configure the device registers based on initialization vector
**                 passed in.  For driver internal use only
**
**  VALID STATES:  Not applicable
**
**  SIDE EFFECTS:  None.
**
**  INPUTS:        u4BaseAddr - base address of the DUPLEX device
**                 eDpxMode - Duplex device mode, 
**                            either DPX_CLK_BIT_SER  or DPX_SCI_MASTER
**                                   or DPX_SCI_ANY_SLAVE
**                 psInitVector - pointer to initialization vector
**
**  OUTPUTS:	   None
**
**  RETURN CODES:  DPX_SUCCESS
**                 DPX_ERR_INDIRECT_CHANNEL_BUSY (timeout for indirect channel
**                                                register access)  
**
*******************************************************************************/
INT4 duplexHWCfgReg(UINT4 u4BaseAddr, eDPX_MODE eDpxMode,
                                       sDPX_INIT_VECTOR *psInitVector)
{
    UINT1 Channel;
    UINT1 u1TxFifoDepth;
    INT4 ErrorCode;

    /* Configure the DUPLEX Control Registers */
	sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_MASTER_CFG), 
	                                      psInitVector->sRegInfo.u1MasterCfg );

    /* SCI-PHY/ANY-PHY registers */
    if(eDpxMode != DPX_CLK_BIT_SER)
    {
        /** This is PHY mode, we need validate the Phy related Initial Vector */
        
        /* check Parity Type consistence between Input/Output SCI-PHY/ANY-PHY */
	    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_EXT_ADDR_MATCH_LSB), 
	                 psInitVector->sRegInfo.sSciAnyPhyRegs.u1ExtAddrMatch[0] );

	    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_EXT_ADDR_MATCH_MSB), 
	                 psInitVector->sRegInfo.sSciAnyPhyRegs.u1ExtAddrMatch[1] );

	    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_EXT_ADDR_MASK_LSB), 
	                  psInitVector->sRegInfo.sSciAnyPhyRegs.u1ExtAddrMask[0] );

	    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_EXT_ADDR_MASK_MSB), 
	                  psInitVector->sRegInfo.sSciAnyPhyRegs.u1ExtAddrMask[1] );

	    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_OUTPUT_ADDR_MATCH), 
	                    psInitVector->sRegInfo.sSciAnyPhyRegs.u1OutAddrMatch );

	    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_PHY_INPUT_CFG1), 
	              psInitVector->sRegInfo.sSciAnyPhyRegs.u1SciAnyPhyInpCfg[0] );

	    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_PHY_INPUT_CFG2), 
	              psInitVector->sRegInfo.sSciAnyPhyRegs.u1SciAnyPhyInpCfg[1] );

	    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_INPUT_CELL_AV_EN_LSB), 
	                    psInitVector->sRegInfo.sSciAnyPhyRegs.u1ICAEnable[0] );

	    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_INPUT_CELL_AV_EN_2ND), 
	                    psInitVector->sRegInfo.sSciAnyPhyRegs.u1ICAEnable[1] );

	    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_INPUT_CELL_AV_EN_3RD), 
	                    psInitVector->sRegInfo.sSciAnyPhyRegs.u1ICAEnable[2] );

	    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_INPUT_CELL_AV_EN_MSB), 
	                    psInitVector->sRegInfo.sSciAnyPhyRegs.u1ICAEnable[3] );

	    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_PHY_OUTPUT_CFG), 
	                 psInitVector->sRegInfo.sSciAnyPhyRegs.u1SciAnyPhyOutCfg );

        sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_PHY_OUTPUT_POLL_RANGE), 
	              psInitVector->sRegInfo.sSciAnyPhyRegs.u1SciAnyPhyOutPollRng );
    }
    else
    {
        /* Clocked Serial Interface registers using indirect channel access
           calls */
        for(Channel = 0; Channel < 16; Channel++)
        {
	        ErrorCode = dpxRxIndChnlWrite(u4BaseAddr, 
                                          DPX_REG_RCV_SER_IND_CHNL_CFG, 
	                                      Channel,
                           psInitVector->sRegInfo.sClkSerRegs.u1RxCfg[Channel]);
            if(ErrorCode != DPX_SUCCESS)
                return(ErrorCode);
            

	        ErrorCode = dpxRxIndChnlWrite(u4BaseAddr, 
                DPX_REG_RCV_SER_LCD_COUNT_THRESHOLD,Channel, 
	            psInitVector->sRegInfo.sClkSerRegs.u1RxLcdCntThresh[Channel] );
            if(ErrorCode != DPX_SUCCESS)
                return(ErrorCode);

	        ErrorCode = dpxTxIndChnlWrite(u4BaseAddr, 
                DPX_REG_TX_SER_IND_CHNL_DATA, Channel, 
                psInitVector->sRegInfo.sClkSerRegs.u1TxSerIndChnlData[Channel]);			
            if(ErrorCode != DPX_SUCCESS)
                return(ErrorCode);

        }

        sysDuplexRawWrite((INT1 *)(u4BaseAddr +