dpx.c

交换机中常用芯片链路复用7350的驱动源代码(vxworks中实现)

**  VALID STATES:  Not applicable
**
**  SIDE EFFECTS:  The device has been software reset.
**
**  INPUTS:		   u4BaseAddr - base address of the DUPLEX device
**
**  OUTPUTS:	   None
**
**  RETURN CODES:  None 
**
*******************************************************************************/

VOID duplexHWReset(UINT4 u4BaseAddr)
{
    UINT1 u1Value;

    /* read in the type and revision number */
    sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_MASTER_RESET_ID), u1Value);
      
    /* reset hold */
    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_MASTER_RESET_ID), 0x80);

    /* waiting for 1 millisecond */
    sysDuplexDelayFn(0x01);

    /* clear the reset */
    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_MASTER_RESET_ID), 0x00);

    /**************************************************************************
    **  For Rev.A, we need call the following function to work around the
    **  low HSS TX power problem 
    **************************************************************************/
    if((u1Value & DPX_MASK_MASTER_ID) == DUPLEX_DEV_ID_REV_A)
        DpxLowTxPowerFix(u4BaseAddr);
     
    return;
}

/*******************************************************************************
**
**  duplexResetFifos
**  ___________________________________________________________________________ 
**
**  DESCRIPTION:   Resets the DUPLEX device FIFOs which include all logical 
**                 channel Rx and Tx FIFOs and Microprocessor port RXD1 and RXD2
**                 Extract FIFOs.  For driver internal use only
**
**  VALID STATES:  Not applicable
**
**  SIDE EFFECTS:  The FIFO are emptied and reset.
**
**  INPUTS:		   u4BaseAddr - base address of the DUPLEX device
**
**  OUTPUTS:	   None
**
**  RETURN CODES:  None 
**
*******************************************************************************/
 VOID duplexResetFifos(UINT4 u4BaseAddr)
 {
 
    UINT1 u1Value; 
	
    /** Tx Logical Channel FOFO **/	
	sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_TX_LC_FIFO_CTL), u1Value);

	/* set the FIFORST bit */
    u1Value |= DPX_MASK_LC_FIFO_CTL_FIFORST;	 
	sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_TX_LC_FIFO_CTL), u1Value);
 
    /* clear the FIFORST bit */
    u1Value &= ~(DPX_MASK_LC_FIFO_CTL_FIFORST);	 
	sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_TX_LC_FIFO_CTL), u1Value);

   
   
    /** Rx Logical Channel FIFO **/
	sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_RCV_LC_FIFO_CTL), u1Value);

	/* set the FIFORST bit */
    u1Value |= DPX_MASK_LC_FIFO_CTL_FIFORST;	 
	sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_RCV_LC_FIFO_CTL), u1Value);
 
    /* clear the FIFORST bit */
    u1Value &= ~(DPX_MASK_LC_FIFO_CTL_FIFORST);	 
	sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_RCV_LC_FIFO_CTL), u1Value);
    
    
    
    /** RXD1 Extract FIFO **/
	sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_RXD1_EFIFO_CTL), u1Value);

	/* set the FIFORST bit */
    u1Value |= DPX_MASK_MICRO_EXTRACT_FIFO_UPFRST;	 
	sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_RXD1_EFIFO_CTL), u1Value);
 
    /* clear the FIFORST bit */
    u1Value &= ~(DPX_MASK_MICRO_EXTRACT_FIFO_UPFRST);	 
	sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_RXD1_EFIFO_CTL), u1Value);

 
    
    
    /** RXD2 Extract FIFO **/
	sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_RXD2_EFIFO_CTL), u1Value);

	/* set the FIFORST bit */
    u1Value |= DPX_MASK_MICRO_EXTRACT_FIFO_UPFRST;	 
	sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_RXD2_EFIFO_CTL), u1Value);
 
    /* clear the FIFORST bit */
    u1Value &= ~(DPX_MASK_MICRO_EXTRACT_FIFO_UPFRST);	 
	sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_RXD2_EFIFO_CTL), u1Value);
    
    return;
 
 }

/*******************************************************************************
**
**  duplexHWtoggleMastIntEn
**  ___________________________________________________________________________ 
**
**  DESCRIPTION:   Set/clear the master interrupt enable bit on or off.
**                 For driver internal use only
**
**  VALID STATES:  Not applicable
**
**  SIDE EFFECTS:  
**
**  INPUTS:		   u4BaseAddr - base address of the DUPLEX device
**                 u1Active - flag to enable/disable the Interrupt
**                            DPX_INACTIVE_LOW: disable it; 
**                            DPX_ACTIVE_HIGH: enable
**
**  OUTPUTS:	   None
**
**  RETURN CODES:  None 
**
*******************************************************************************/

VOID duplexHWtoggleMastIntEn(UINT4 u4BaseAddr, UINT1 u1Active)
{
    UINT1 u1Value; 
		
    /* peek */
	sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_MASTER_CFG), u1Value);

	/* set or clear the MINTE bit */
    if(u1Active == DPX_ACTIVE_HIGH)
    	u1Value |= DPX_MASK_MASTER_CFG_MINTE;	 /* set */
    else
        u1Value &= (~DPX_MASK_MASTER_CFG_MINTE);  /* clear */

    /* poke */
	sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_MASTER_CFG), u1Value);

    
}

/*******************************************************************************
**
**  duplexHWDevMode
**  ___________________________________________________________________________ 
**
**  DESCRIPTION:   determine the DUPLEX device mode based on Configuration Pins
**                 Status Register settings.  For driver internal use only
**
**  VALID STATES:  Not applicable
**
**  SIDE EFFECTS:  None.
**
**  INPUTS:		   u4BaseAddr - base address of the DUPLEX device
**
**  OUTPUTS:	   None
**
**  RETURN CODES:  DPX mode
**                 DPX_MODE_UNKNOWN;
**                 DPX_SCI_MASTER;
**                 DPX_SCI_ANY_SLAVE;
**                 DPX_CLK_BIT_SER.
**
*******************************************************************************/
eDPX_MODE duplexHWDevMode(UINT4 u4BaseAddr)
{
     UINT1 u1CfgVal = 0;
     eDPX_MODE eDpxMode = DPX_MODE_UNKNOWN;

     /* read in the  Configuration Pins Status Register	*/
	 sysDuplexRawRead((INT1 *)(u4BaseAddr+DPX_REG_CFG_PINS_STATUS), u1CfgVal);

	/* determine its mode based on its Input pins */
	if(u1CfgVal & DPX_MASK_CFG_PINS_SCIANYV) 
	{
	   /* SCI-PHY or ANY-PHY interface is used */
	   if(u1CfgVal & DPX_MASK_CFG_PINS_IMASTERV)
	      eDpxMode = DPX_SCI_MASTER;
	   else
	      eDpxMode = DPX_SCI_ANY_SLAVE;
    }
	else
	{
	    eDpxMode = DPX_CLK_BIT_SER;	 /* Clocked Serial Data Interface */
		
    }

    return eDpxMode;
}



/*******************************************************************************
**
**  dpxRxIndChnlWrite
**  ___________________________________________________________________________ 
**
**  DESCRIPTION:   Write a value into Receive Indirect Channel registers.  
**                 For driver internal use only
**
**  VALID STATES:  Not applicable
**
**  SIDE EFFECTS:  None.
**
**  INPUTS:		   u4BaseAddr - base address of the DUPLEX device
**                 u1RegID - address offset for Rx Indirect Channel registers
**                 u1ChannelID - channel number
**                 u1Value - the value to be written
**
**  OUTPUTS:	   None
**
**  RETURN CODES:  DPX_SUCCESS
**                 DPX_ERR_INDIRECT_CHANNEL_BUSY (timeout for indirect channel
**                                                access) 
**
*******************************************************************************/
  
INT4 dpxRxIndChnlWrite(UINT4 u4BaseAddr, UINT1 u1RegID, UINT1 u1ChannelID, 
                                                                  UINT1 u1Value) 
{
    UINT1 u1Select = 0;
    UINT4 i = 0;

	/* check and wait for the Indirect Access Busy bit to be cleared */
	do 
	{
	   sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_RCV_SER_IND_CHNL_SELECT), 
	                       u1Select);
       i++;
       if(i > DPX_IND_CHNL_TIMEOUT)
            return(DPX_ERR_INDIRECT_CHANNEL_BUSY);
        
	}
	while (u1Select & DPX_MASK_IND_CHNL_SELECT_CBUSY);
	
    /* write the content into Receive Clocked Serial Registers */
    sysDuplexRawWrite((INT1 *)(u4BaseAddr + u1RegID), u1Value);

    /* select the channel and clear CRWB bit to trigger a write operation */
    u1Select &= DPX_MASK_IND_CHNL_SELECT_DRHCSE; /* keep the DRHCSE bit */
	u1Select |= (u1ChannelID & ~DPX_MASK_IND_CHNL_SELECT_CRWB); 
    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_RCV_SER_IND_CHNL_SELECT), 
                                                                      u1Select);

	/* wait for the write operation to be completed */
    i = 0;
	do 
	{
	   sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_RCV_SER_IND_CHNL_SELECT), 
	                       u1Select);
       i++;
       if(i > DPX_IND_CHNL_TIMEOUT)
            return(DPX_ERR_INDIRECT_CHANNEL_BUSY);

	}
	while (u1Select & DPX_MASK_IND_CHNL_SELECT_CBUSY);
    
    return(DPX_SUCCESS);

}

/*******************************************************************************
**
**  dpxRxIndChnlRead
**  ___________________________________________________________________________ 
**
**  DESCRIPTION:   Read a value from a Receive Indirect Channel register.  
**                 For driver internal use only
**
**  VALID STATES:  Not applicable
**
**  SIDE EFFECTS:  None.
**
**  INPUTS:		   u4BaseAddr - base address of the DUPLEX device
**                 u1RegID - address offset for Rx Indirect Channel register
**                 u1ChannelID - channel number (0 to 15)
**
**  OUTPUTS:	   pu1Value - pointer to the value read
**
**  RETURN CODES:  DPX_SUCCESS
**                 DPX_ERR_INDIRECT_CHANNEL_BUSY (timeout for indirect channel
**                                                access)  
**
*******************************************************************************/
INT4 dpxRxIndChnlRead(UINT4 u4BaseAddr, UINT1 RegID, UINT1 ChannelID, 
                                                               UINT1 *pu1Value) 
{
    UINT1 u1Select = 0;
    UINT4 i = 0;

	/*  wait for interface to be available i.e. the Indirect Access Busy bit 
	    should be cleared */
	do 
	{
	   sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_RCV_SER_IND_CHNL_SELECT), 
	                       u1Select);
	   i++;
       if(i > DPX_IND_CHNL_TIMEOUT)
            return(DPX_ERR_INDIRECT_CHANNEL_BUSY);

    }
	while (u1Select & DPX_MASK_IND_CHNL_SELECT_CBUSY);

	u1Select &= DPX_MASK_IND_CHNL_SELECT_DRHCSE; /* keep the DRHCSE bit */
	
    /* select the channel and set CRWB bit to trigger a read operation */
	u1Select |= (ChannelID | DPX_MASK_IND_CHNL_SELECT_CRWB); 
    sysDuplexRawWrite((INT1 *)(u4BaseAddr + DPX_REG_RCV_SER_IND_CHNL_SELECT), 
                                                                      u1Select);

	/*  wait for the Indirect Access Busy bit to be cleared */
    i = 0;
	do 
	{
	   sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_RCV_SER_IND_CHNL_SELECT), 
	                       u1Select);
	   i++;
       if(i > DPX_IND_CHNL_TIMEOUT)
            return(DPX_ERR_INDIRECT_CHANNEL_BUSY);

    }
	while (u1Select & DPX_MASK_IND_CHNL_SELECT_CBUSY);

    /* Ok, read the value now */
	sysDuplexRawRead((INT1 *)(u4BaseAddr + RegID), *pu1Value);
    return(DPX_SUCCESS);
    

}

/*******************************************************************************
**