📄 dpx.c
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/* Receive Logical Channel FIFO interrupt status:
the status bits are cleared after the read */
sysDuplexRawRead((INT1 *)(u4BaseAddr +DPX_REG_RCV_LC_FIFO_INT_STATUS),
u1LcFifoIntStatus);
if(u1LcFifoIntStatus & DPX_MASK_LC_FIFO_INT_STATUS_FOVRI)
{
/* Rx logical channel FIFO overflow */
(psDpxDdb->sStatCounts.Count_Rx_Lc_Fifo_Overflow)++;
pDpxEventNotify(psDpxDdb,DPX_EVENT_RX_LC_FIFO_OVERFLOW,
u1LcFifoIntStatus, 0, DPX_NULL);
}
}
if(u1MasterINTStatus & DPX_MASK_MASTER_INT_STATUS_TFI)
{
/* Tx Logical Channel FIFO interrupt status:
the status bits are cleared after the read */
sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_TX_LC_FIFO_INT_STATUS),
u1LcFifoIntStatus);
if(u1LcFifoIntStatus & DPX_MASK_LC_FIFO_INT_STATUS_FOVRI)
{
/* Tx logical channel FIFO overflow */
(psDpxDdb->sStatCounts.Count_Tx_Lc_Fifo_Overflow)++;
pDpxEventNotify(psDpxDdb,DPX_EVENT_TX_LC_FIFO_OVERFLOW,
u1LcFifoIntStatus, 0, DPX_NULL);
}
}
if(u1MasterINTStatus & DPX_MASK_MASTER_INT_STATUS_ICIFI)
{
/* SCI-PHY/ANY-PHY Input interrupt status:
the status bits are cleared after the read */
sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_PHY_INPUT_INT_STATUS),
u1PhyIntStatus);
if(u1PhyIntStatus & DPX_MASK_PHY_INPUT_INT_STATUS_PHYCELLI)
{
/* a physical cell is transferred over the PHY input port */
(psDpxDdb->sStatCounts.Count_Phy_Input_Cell_Xfered)++;
pDpxEventNotify(psDpxDdb,DPX_EVENT_PHY_INPUT_CELL_XFERED,
u1PhyIntStatus, 0, DPX_NULL);
}
if(u1PhyIntStatus & DPX_MASK_PHY_INPUT_INT_STATUS_CELLXFERRI)
{
/* an invalid start of cell (SOC) sequence is detected */
(psDpxDdb->sStatCounts.Count_Invalid_SOC_Sequence)++;
pDpxEventNotify(psDpxDdb,DPX_EVENT_INVALID_SOC_SEQUENCE,
u1PhyIntStatus, 0, DPX_NULL);
}
if(u1PhyIntStatus & DPX_MASK_PHY_INPUT_INT_STATUS_PARERRI)
{
/* a parity error is detected */
(psDpxDdb->sStatCounts.Count_Phy_Input_Parity)++;
pDpxEventNotify(psDpxDdb,DPX_EVENT_PHY_INPUT_PARITY,
u1PhyIntStatus, 0, DPX_NULL);
}
}
if(u1MasterINTStatus & DPX_MASK_MASTER_INT_STATUS_OCIFI)
{
/* SCI-PHY/ANY-PHY Output interrupt status:
the status bits are cleared after the read */
sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_PHY_OUTPUT_CFG),
u1PhyIntStatus);
if(u1PhyIntStatus & DPX_MASK_PHY_OUTPUT_CFG_CELLXFERRI)
{
/* Tx cell transfer error: an external master device selects the
PHY interface output port for a transfer without a cell being
available */
(psDpxDdb->sStatCounts.Count_Phy_Output_Error)++;
pDpxEventNotify(psDpxDdb,DPX_EVENT_PHY_OUTPUT_ERROR,
u1PhyIntStatus, 0, DPX_NULL);
}
}
if(u1MasterINTStatus & DPX_MASK_MASTER_INT_STATUS_UPCIFI)
{
/* Microprocessor Cell Interface interrupt status:
the status bits are cleared after the read */
sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_MICRO_CELL_BUFF_INT),
u1MicroIntStatus);
/* work around the problem that, clearing the INSRDYE bit doesn't
mask the INSRDYI bit */
if((u1MicroIntStatus & DPX_MASK_MICRO_CELL_BUFF_INT_INSRDYI) &&
(u1MicroIntStatus & DPX_MASK_MICRO_CELL_BUFF_INT_INSRDYE ))
{
/* Insert FIFO becomes ready to accept a cell */
(psDpxDdb->sStatCounts.Count_Micro_Insert_Fifo_Ready)++;
pDpxEventNotify(psDpxDdb,DPX_EVENT_MICRO_INSERT_FIFO_READY,
u1MicroIntStatus, 0, DPX_NULL);
}
if(u1MicroIntStatus & DPX_MASK_MICRO_CELL_BUFF_INT_INSOVRI)
{
/* writing to a full Insert FIFO, and cell data discarded */
(psDpxDdb->sStatCounts.Count_Micro_Insert_Fifo_Full)++;
pDpxEventNotify(psDpxDdb,DPX_EVENT_MICRO_INSERT_FIFO_FULL,
u1MicroIntStatus, 0, DPX_NULL);
}
if(u1MicroIntStatus & DPX_MASK_MICRO_CELL_BUFF_INT_EXTRDYI)
{
/* Extract FIFO becomes ready for a cell read */
(psDpxDdb->sStatCounts.Count_Extract_Cells)++;
/* Disable the Extract Cell indication/interrupt. It will be turned
on after all the Rx cells extracted by calling duplexEnableRxInd
*/
duplexClearRegBits(u4BaseAddr,
DPX_REG_MICRO_CELL_BUFF_INT,
DPX_MASK_MICRO_CELL_BUFF_INT_EXTRDYE);
/** call user-supplied indication callback routine **/
if(psDpxDdb->indRxCell != DPX_NULL)
psDpxDdb->indRxCell(psDpxDdb->usrCtxt, DPX_NULL);
}
if(u1MicroIntStatus & DPX_MASK_MICRO_CELL_BUFF_INT_EXTCRCERRI)
{
/* cell read from Extract FIFO has CRC error */
(psDpxDdb->sStatCounts.Count_Extract_Cell_CRC_Error)++;
pDpxEventNotify(psDpxDdb,DPX_EVENT_EXTRACT_CELL_CRC_ERROR,
u1MicroIntStatus, 0, DPX_NULL);
}
}
}
/*******************************************************************************
**
** pDpxProcMiscIntStatus
** ___________________________________________________________________________
**
** DESCRIPTION: This routine is called by the duplexDPR when the device
** gets Miscalenous interrupt events. The function processes
** each bit in the Miscalenous interrupt status register
**
**
** VALID STATES: Not applicable
**
** SIDE EFFECTS:
**
** INPUTS: u1MiscIntStatus - value read from Miscalenous Interrupt Status
** register
** psDpxDdb - device handlerr.
**
** OUTPUTS: None
**
** RETURN CODES: None
**
*******************************************************************************/
VOID pDpxProcMiscIntStatus(sDPX_DDB *psDpxDdb, UINT1 u1MiscIntStatus)
{
UINT1 u1ClockMonitorStatus = 0;
UINT1 u1RxBocStatus = 0;
UINT1 Channel, HssId;
UINT1 u1RxSerIndChnlIntStatus = 0;
UINT1 u1RxExtractFifoStatus = 0;
UINT4 u4BaseAddr;
u4BaseAddr = psDpxDdb->u4BaseAddr;
/*****************************************************
** check each Miscellaneous interrupt status bits **
******************************************************/
if(u1MiscIntStatus & DPX_MASK_MISC_INT_STATUS_ROOLI)
{
/* Clock Monitor register has changed state */
sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_CLOCK_MONITOR),
u1ClockMonitorStatus);
if(u1ClockMonitorStatus & DPX_MASK_CLOCK_MONITOR_ROOLV)
{
/* clock out of lock */
(psDpxDdb->sStatCounts.Count_Clock_Lock_Fail)++;
pDpxEventNotify(psDpxDdb,DPX_EVENT_CLOCK_LOCK_FAIL,
u1ClockMonitorStatus, 0, DPX_NULL);
}
}
if(u1MiscIntStatus & DPX_MASK_MISC_INT_STATUS_RBOCI)
{
/* RXD1 BOC interrupt */
sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_RXD1_BOC_STATUS),
u1RxBocStatus);
if(u1RxBocStatus & DPX_MASK_BOC_RCV_STATUS_IND_BITS)
{
(psDpxDdb->sStatCounts.Count_Rx_BOCs[0])++;
pDpxProcessRxBOC(psDpxDdb,DPX_RXD1, u1RxBocStatus);
}
/* RXD2 BOC interrupt */
sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_RXD2_BOC_STATUS),
u1RxBocStatus);
if(u1RxBocStatus & DPX_MASK_BOC_RCV_STATUS_IND_BITS)
{
(psDpxDdb->sStatCounts.Count_Rx_BOCs[1])++;
pDpxProcessRxBOC(psDpxDdb, DPX_RXD2, u1RxBocStatus);
}
}
if(u1MiscIntStatus & DPX_MASK_MISC_INT_STATUS_RCSDI)
{
/* RX Clocked Serial Data Interface interrupt */
for(Channel = 0; Channel < 16; Channel++)
{
dpxRxIndChnlRead(u4BaseAddr, DPX_REG_RCV_SER_IND_CHNL_INT_STATUS,
Channel, &u1RxSerIndChnlIntStatus);
if(u1RxSerIndChnlIntStatus &
DPX_MASK_RCV_SER_IND_CHNL_INT_STATUS_LCDI)
{
/* Loss of cell delineation state changed */
if(u1RxSerIndChnlIntStatus &
DPX_MASK_RCV_SER_IND_CHNL_INT_STATUS_LCDV)
{
/* Out of Cell Delineation defect has persisted for the
number of cells specified in the LCD Count Threshold
register */
(psDpxDdb->sStatCounts.Count_RxSerChnl_Out_Of_Delin[Channel])++;
pDpxEventNotify(psDpxDdb,
DPX_EVENT_RX_SER_CHNL_OUT_OF_DELIN,
u1RxSerIndChnlIntStatus, 1, &Channel);
}
else
{
(psDpxDdb->sStatCounts.Count_RxSerChnl_In_Delin[Channel])++;
pDpxEventNotify(psDpxDdb,DPX_EVENT_RX_SER_CHNL_IN_DELIN,
u1RxSerIndChnlIntStatus, 1, &Channel);
}
}
if(u1RxSerIndChnlIntStatus &
DPX_MASK_RCV_SER_IND_CHNL_INT_STATUS_FOVRI)
{
/* FIFO overrun */
(psDpxDdb->sStatCounts.Count_RxSerChnl_Fifo_Overflow[Channel])++;
pDpxEventNotify(psDpxDdb,DPX_EVENT_RX_SER_CHNL_FIFO_OVERFLOW,
u1RxSerIndChnlIntStatus, 1, &Channel);
}
if(u1RxSerIndChnlIntStatus &
DPX_MASK_RCV_SER_IND_CHNL_INT_STATUS_HCSI)
{
/* HCS error detected */
(psDpxDdb->sStatCounts.Count_RxSerChnl_HCS_Error[Channel])++;
pDpxEventNotify(psDpxDdb,DPX_EVENT_RX_SER_CHNL_HCS_ERROR,
u1RxSerIndChnlIntStatus, 1, &Channel);
}
if(u1RxSerIndChnlIntStatus &
DPX_MASK_RCV_SER_IND_CHNL_INT_STATUS_OOCDI)
{
/* Cell Delineation state machine enters/exits the SYNC state */
if(u1RxSerIndChnlIntStatus &
DPX_MASK_RCV_SER_IND_CHNL_INT_STATUS_OOCDV)
{
/* cell delineation state machine is in the "HUNT" or
"PRESYNC" state */
(psDpxDdb->sStatCounts.Count_RxSerChnl_Out_Of_Sync[Channel])++;
pDpxEventNotify(psDpxDdb,
DPX_EVENT_RX_SER_CHNL_OUT_OF_SYNC,
u1RxSerIndChnlIntStatus, 1, &Channel);
}
else
{
/* Signal transition detected */
(psDpxDdb->sStatCounts.Count_RxSerChnl_in_Sync[Channel])++;
pDpxEventNotify(psDpxDdb,DPX_EVENT_RX_SER_CHNL_IN_SYNC,
u1RxSerIndChnlIntStatus, 1, &Channel);
}
}
} /* for */
}
if(u1MiscIntStatus & DPX_MASK_MISC_INT_STATUS_UPFI)
{
/* Microprocessor Extract FIFO Interrupt */
/** RXD1 **/
sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_RXD1_EFIFO_INT_STATUS),
u1RxExtractFifoStatus);
if(u1RxExtractFifoStatus & DPX_MASK_MICRO_EXTRACT_FIFO_UPFOVRI)
{
/* RXD1 Extract FIFO overflow error */
(psDpxDdb->sStatCounts.Count_RxHss_Extract_Fifo_Overflow[0])++;
HssId = DPX_RXD1;
pDpxEventNotify(psDpxDdb,DPX_EVENT_RX_EXTRACT_FIFO_OVERFLOW,
u1RxExtractFifoStatus, 1, &HssId);
}
/** RXD2 **/
sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_RXD2_EFIFO_INT_STATUS),
u1RxExtractFifoStatus);
if(u1RxExtractFifoStatus & DPX_MASK_MICRO_EXTRACT_FIFO_UPFOVRI)
{
/* RXD2 Extract FIFO overflow error */
(psDpxDdb->sStatCounts.Count_RxHss_Extract_Fifo_Overflow[1])++;
HssId = DPX_RXD2;
pDpxEventNotify(psDpxDdb,DPX_EVENT_RX_EXTRACT_FIFO_OVERFLOW,
u1RxExtractFifoStatus, 1, &HssId);
}
}
}
/*******************************************************************************
**
** pDpxEventNotify
** ___________________________________________________________________________
**
** DESCRIPTION: This routine is called by the duplexDPR when the device
** gets an event. It trys to set up an indication buffer and calls
** user supplied callback routine "indNotify()". For driver
** internal use.
**
**
** VALID STATES: Not applicable
**
** SIDE EFFECTS:
**
** INPUTS: psDpxDdb - pointer to the device DDB.
** eEventId - event ID
** len - the byte length of supplement field pointed by pSupplement
** pSupplement - contains the supplemental information about the event
**
** OUTPUTS: None
**
** RETURN CODES: None
**
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