dpx.c

交换机中常用芯片链路复用7350的驱动源代码(vxworks中实现)

/******************************************************************************/
/**  COPYRIGHT (C) 1999 PMC-SIERRA, INC. ALL RIGHTS RESERVED.                **/
/**--------------------------------------------------------------------------**/
/** This software embodies materials and concepts which are proprietary and  **/
/** confidential to PMC-Sierra, Inc.                                         **/
/** PMC-Sierra distributes this software to its customers pursuant to the    **/ 
/** terms and conditions of the Device Driver Software License Agreement     **/ 
/** contained in the text file software.lic that is distributed along with   **/ 
/** the device driver software. This software can only be utilized if all    **/ 
/** terms and conditions of the Device Driver Software License Agreement are **/ 
/** accepted. If there are any questions, concerns, or if the Device Driver  **/
/** Software License Agreement text file, software.lic, is missing please    **/
/** contact PMC-Sierra for assistance.                                       **/
/**--------------------------------------------------------------------------**/
/**                                                                          **/
/******************************************************************************/
/*******************************************************************************
**    MODULE     : Duplex device drivers source file specific to Duplex device
**
**    FILE       : Dpx.c
**      
**    DESCRIPTION: This file contains Duplex device driver utility function.
**                 Primarily for driver internal use.
**
**
**    NOTES      :
**
*******************************************************************************/
/* 
**    MODIFICATION HISTORY:
**
** $Log: dpx.c.rca $
** 
**  Revision: 1.1 Wed Aug 16 16:22:15 2000 bhalwani
**    Beta-1.0
**
** 
**  4   06/15/00    Bhalwani        Vortex chipset driver beta-1.0
**  3   06/15/00    Bhalwani        Vortex chipset driver Alpha-1.30
**  2   04/07/00    chenkemi        added FIFO reset
**  1   07/16/99    chenkemi        Initial Version
**
**  22  04/07/00    chenkemi        added FIFO reset routine
**  21  07/16/99    chenkemi        Beta-1.0
**  20  07/16/99    chenkemi        implemented new LVDS fix
**  19  07/13/99    chenkemi        added addendum to the DpxLowTxPowerFix() per Kelly.
**  18  07/02/99    chenkemi        renamed DUPLEX_DEV_ID
**  17  06/30/99    chenkemi        implemented new fix for the Tx Power bug
**  16  06/29/99    chenkemi        fixed a bug in dpxTxIndChnlRead nad dpxTxIndChnlWrite
**  15  06/28/99    chenkemi        added code for Rev.A bug fix
**  14  06/17/99    chenkemi        removed u1TxFifoDepth from sDPX_HSS_REGS structure.
**  13  06/16/99    chenkemi        Fixed CRC-32 read/write routines
**  12  06/02/99    chenkemi        renamed the compile switch DPX_INTERRUPT_MODE to 
**                                  DPX_CSW_INTERRUPT_MODE
**  11  05/28/99    chenkemi        added "pDpxProcMasterIntStatus" and 
**                                  "pDpxProcMiscIntStatus" functions.
**  10  05/26/99    chenkemi        code cleanup after code review.
**  9   04/26/99    chenkemi        changed flag usage in "duplexTogglebit()"
**  8   04/12/99    chenkemi        added access timeout for "indirect serial channel"  
**                                  registers.
**  7   04/12/99    chenkemi        changed "#ifdef CSW_PV_FLAG" to "#if CSW_PV_FLAG".
**  6   04/09/99    chenkemi        reorganized the file : fit to length limit
**  5   03/31/99    chenkemi        removed u4dpxROOLCount variable
**  4   03/29/99    chenkemi        added statistical couns data structure and API.
**  3   03/19/99    chenkemi        Version Alpha1.1
**  2   03/10/99    chenkemi        Fixed interrupt bug, and added more API functions
**  1   03/02/99    chenkemi        Initial Version
**
*/


/** include files **/
#include "dpx_api.h"
#include "dpx.h"


/** external functions **/

/** external data **/
extern sDPX_GDD         *psDpxGdd;

/** public data **/

/** public functions **/

/** private data **/

/** private functions **/


#if DPX_CSW_INTERRUPT_MODE   /** Interrupt mode **/
/*******************************************************************************
**
**  duplexISR
**  ___________________________________________________________________________ 
**
**  DESCRIPTION: It reads the top level interrupt status registers of the 
**               interrupting device. If there any bits set in these registers, 
**               this routine returns a value greater than 0. If there are no 
**               bits set, this routine returns a 0.
**               This routine is invoked by the system specific interrupt handler
**               routine, sysDuplexIntHandler
**               
**
**  VALID STATES:  DPX_ACTIVE
**
**  SIDE EFFECTS: If the function returns with a non-zero value, i.e., interrupt
**                condition(s) have been detected, all device interrupts are 
**                disabled.
**
**  INPUTS:	     duplex - pointer to the device DDB.
**
**  OUTPUTS:	 None
**
**  RETURN CODES: 0, no valid interrupt conditions detected.
**                1, at least one valid interrupt condition detected.
**
*******************************************************************************/

UINT4 duplexISR(DUPLEX duplex)
{
    UINT1 u1MasterIntStatus = 0;
    UINT1 u1MiscIntStatus = 0;
    UINT1 u1ClockMonitorStatus = 0;
    UINT4 u4BaseAddr;
    sDPX_DDB *psDpxDdb;

    psDpxDdb = (sDPX_DDB *)duplex;
    u4BaseAddr = psDpxDdb->u4BaseAddr;
    
    /* read in the Master Interrupt Status register */
    sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_MASTER_INT_STATUS), 
	                       u1MasterIntStatus);

    /* read in Miscellaneous Interrupt Status register */
    sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_MISC_INT_STATUS), 
	                       u1MiscIntStatus);

    
    /* check if there is any bits set */                      
    if(u1MasterIntStatus)
    {
        /* disable the Master Interrupt Enable bit. It 
           will be re-enabled in the sysDuplexDPRtask process */
        duplexHWtoggleMastIntEn(u4BaseAddr, DPX_INACTIVE_LOW);
        
        /* reset the u1IntProcEn flag */
        psDpxDdb->u1IntrProcEn = 0; 
 
    	return 1;
    }
        
    else if(u1MiscIntStatus)
    {
        if(u1MiscIntStatus & DPX_MASK_MISC_INT_STATUS_ROOLI)
        {
            /* Clock Monitor register has changed state */
            sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_CLOCK_MONITOR), 
	                       u1ClockMonitorStatus);
            if(u1ClockMonitorStatus & DPX_MASK_CLOCK_MONITOR_ROOLV)
            {
              /* clock out of lock */
              /* increment statistic value for Reference Out-of-lock count */
              (psDpxDdb->sStatCounts.Count_Clock_Lock_Fail)++;
            }
         }

        if(u1MiscIntStatus & 0x0F)        
        {
        
            /* disable the Master Interrupt Enable bit. It 
                will be re-enabled in the sysDuplexDPRtask process */
            duplexHWtoggleMastIntEn(u4BaseAddr, DPX_INACTIVE_LOW);
        
            /* reset the u1IntProcEn flag */
            psDpxDdb->u1IntrProcEn = 0; 
            return 1;
        }
        else
     	   return 0;  /* no bits set */
    }
    return 0;
}
#endif


/*******************************************************************************
**
**  duplexDPR
**  ___________________________________________________________________________ 
**
**  DESCRIPTION: Reads the device interrupt status registers, clears the 
**               interrupt conditions and invokes user-defined callback functions
**               to perform system-specific processing based on the interrupt 
**               conditions detected.
**               This function is invoked by the system specific DPR task 
**               routine, sysDuplexDPRtask.             
**
**  VALID STATES:  DPX_ACTIVE
**
**  SIDE EFFECTS:  In INTERRUPT mode: Enables device interrupts after 
**                 processing all the existing interrupt conditions. 
**                 In POLLING mode: Master interrupt bit is not changed after 
**                 processing
**
**  INPUTS:	     duplex	- pointer to the device DDB data structure
**
**  OUTPUTS:	 None
**
**  RETURN CODES: None
**
*******************************************************************************/
VOID duplexDPR(DUPLEX duplex) 
{    
    UINT1 u1MasterINTStatus = 0;
    UINT1 u1MiscIntStatus = 0;
    sDPX_DDB *psDpxDdb;
    UINT4 u4BaseAddr;
     
    psDpxDdb = (sDPX_DDB *)duplex;

    u4BaseAddr = psDpxDdb->u4BaseAddr;
  

    /* get the semaphore for the sDPX_STAT_COUNT data structure */
    sysDuplexSemTake(psDpxDdb->lockId);
    (psDpxDdb->sStatCounts.Count_Interrupts)++;
      
    /* read in the Master and Miscellaneous Interrupt Status register */
    sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_MASTER_INT_STATUS), 
	                       u1MasterINTStatus);

    sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_MISC_INT_STATUS), 
	                       u1MiscIntStatus);
    
    /** processing the Master interrupt status **/                       
    if(u1MasterINTStatus)
        pDpxProcMasterIntStatus(psDpxDdb, u1MasterINTStatus);
    
    /** processing the Miscellaneous interrupt status **/    
    if(u1MiscIntStatus & DPX_MASK_MISC_INT_STATUS)
        pDpxProcMiscIntStatus(psDpxDdb, u1MiscIntStatus);

     /* release the semaphore lock */
     sysDuplexSemGive(psDpxDdb->lockId);
  
#if DPX_CSW_INTERRUPT_MODE   /** Interrupt mode **/        
     /* set the u1IntProcEn flag !! */
     psDpxDdb->u1IntrProcEn = 1; 

     /* enable the Master Interrupt */
     duplexHWtoggleMastIntEn(u4BaseAddr, DPX_ACTIVE_HIGH);
#endif
   
}

/*******************************************************************************
**
**  pDpxProcMasterIntStatus
**  ___________________________________________________________________________ 
**
**  DESCRIPTION: This routine is called by the duplexDPR when the device 
**               gets Master interrupt events. The function processes
**               each bit in the Master interrupt status register
**               
**
**  VALID STATES:  Not applicable
**
**  SIDE EFFECTS: 
**
**  INPUTS:	  u1MasterIntStatus	- value read from Miscalenous Interrupt Status 
**                                register
**            psDpxDdb - device handlerr.
**
**  OUTPUTS:	 None
**
**  RETURN CODES: None
**
*******************************************************************************/

VOID pDpxProcMasterIntStatus(sDPX_DDB *psDpxDdb, UINT1 u1MasterINTStatus)
{
    UINT1 u1HSSIntStatus = 0;
    UINT1 u1HSSCellStatus = 0;
    UINT1 u1HSSCellCountStatus = 0;
    UINT1 u1LcFifoIntStatus = 0;
    UINT1 u1PhyIntStatus = 0;
    UINT1 u1MicroIntStatus = 0;
    UINT4 u4BaseAddr;

    u4BaseAddr = psDpxDdb->u4BaseAddr;
    
    /*****************************************************
     **  check each Master interrupt status bits         **
     ******************************************************/
    if(u1MasterINTStatus & DPX_MASK_MASTER_INT_STATUS_RX1I) 
    { 
         /* RXD1 HSS interrupt status: the status bits cleared after the read */
         sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_RXD1_HSS_INT_STATUS), 
	                       u1HSSIntStatus);

         /* read in current RxD1 HSS status too */
         sysDuplexRawRead((INT1 *)(u4BaseAddr + 
                            DPX_REG_RXD1_HSS_CELL_FILT_CFG_STATUS), 
	                        u1HSSCellStatus);
 
         pDpxProcessRxHssInt(psDpxDdb,DPX_RXD1,u1HSSIntStatus, u1HSSCellStatus);
     }

     if(u1MasterINTStatus & DPX_MASK_MASTER_INT_STATUS_RX2I) 
     { 
         /* RXD2 HSS interrupt status: the status bits cleared after the read */
         sysDuplexRawRead((INT1 *)(u4BaseAddr + DPX_REG_RXD2_HSS_INT_STATUS), 
	                       u1HSSIntStatus);

         /* read in current RxD2 HSS status too */
         sysDuplexRawRead((INT1 *)(u4BaseAddr + 
                            DPX_REG_RXD2_HSS_CELL_FILT_CFG_STATUS), 
	                        u1HSSCellStatus);
 
         pDpxProcessRxHssInt(psDpxDdb,DPX_RXD2,u1HSSIntStatus, u1HSSCellStatus);
     }
 
     if(u1MasterINTStatus & DPX_MASK_MASTER_INT_STATUS_TXI) 
     { 
         /* Tx HSS interrupt status: the status bits cleared after the read */
         sysDuplexRawRead((INT1 *)(u4BaseAddr + 
                            DPX_REG_TX_HSS_CELL_COUNT_STATUS), 
	                        u1HSSCellCountStatus);
         if(u1HSSCellCountStatus & DPX_MASK_HSS_TX_CELL_COUNT_STATUS_OVR)
         {
             /* Tx Cell Count register has been overwritten */
             (psDpxDdb->sStatCounts.Count_Tx_Hss_Count_Overflow)++;
             pDpxEventNotify(psDpxDdb,DPX_EVENT_TX_HSS_COUNT_OVERFLOW,
                             u1HSSCellCountStatus, 0, DPX_NULL); 
         }

         if(u1HSSCellCountStatus & DPX_MASK_HSS_TX_CELL_COUNT_STATUS_XFERI)
          {
               /* Counter registers has been updated */
               (psDpxDdb->sStatCounts.Count_Tx_Hss_Count_Updated)++;
               pDpxEventNotify(psDpxDdb,DPX_EVENT_TX_HSS_COUNT_UPDATED, 
                               u1HSSCellCountStatus, 0, DPX_NULL);

               /* it's time to read in the Counter register !! */
          }

      }
  
      if(u1MasterINTStatus & DPX_MASK_MASTER_INT_STATUS_RFI) 
      {