📄 dpx.h
字号:
/* define bit mask for RXD1/RXD2 HSS Interrupt Status register (0x43, 0x53) */
/** Bit 0: LOSV bit state change **/
/** Bit 1: LCDV bit change state **/
/** Bit 2: ACTV bit change state **/
/** Bit 3: CRC-8 non-zero error **/
/** Bit 4: HCS error detected **/
/** Bit 5: delineation state enter/exit SYNC **/
/** Bit 6: rcv cell counter or error counter updated **/
/** Bit 7: overrun of counter registers **/
#define DPX_MASK_HSS_INT_STATUS_LOSI 0x01
#define DPX_MASK_HSS_INT_STATUS_LCDI 0x02
#define DPX_MASK_HSS_INT_STATUS_ACTI 0x04
#define DPX_MASK_HSS_INT_STATUS_CELLERRI 0x08
#define DPX_MASK_HSS_INT_STATUS_OCDI 0x10
#define DPX_MASK_HSS_INT_STATUS_HCSI 0x20
#define DPX_MASK_HSS_INT_STATUS_XFERI 0x40
#define DPX_MASK_HSS_INT_STATUS_OVR 0x80
/* define bit mask for Tx Logical Channel FIFO Control register (0x5C) */
/** see register 0x3C mask definition **/
/* define bit mask for Tx Logical Channel FIFO Depth registers (0x5E) */
/** Bit 0-5: number of available cells per logical channel of the TX FIFO **/
#define DPX_MASK_TX_LC_FIFO_DEPTH 0x3F
/* define bit mask for Tx Logical Channel FIFO Ready Level registers (0x5F) */
/** Bit 0-5: set the level at which a
logical channel of the TX FIFO becomes available for write access **/
#define DPX_MASK_TX_LC_FIFO_READY_LEVEL 0x3F
/* define bit mask for Tx HSS Configuration register (0x60) */
/** Bit 0-1: User Header length expected **/
/** Bit 2: User prepend expected **/
/** Bit 3: CRC-8 protected: first user perpend **/
/** Bit 4: HCS octet insertion **/
/** Bit 6: Header Scramble enable **/
/** Bit 7: Disable Scramble **/
#define DPX_MASK_HSS_TX_CFG_USRHDR 0x03
#define DPX_MASK_HSS_TX_CFG_PREPEND 0x04
#define DPX_MASK_HSS_TX_CFG_CELLCRC 0x08
#define DPX_MASK_HSS_TX_CFG_DHCS 0x10
#define DPX_MASK_HSS_TX_CFG_HSCR 0x40
#define DPX_MASK_HSS_TX_CFG_DSCR 0x80
/* define bit mask for Tx HSS Cell Count Status register (0x61) */
/** Bit 5: TX cell Count overrun **/
/** Bit 6: Tx cell count updated **/
/** Bit 7: Int Enable for XFERI **/
#define DPX_MASK_HSS_TX_CELL_COUNT_STATUS_OVR 0x20
#define DPX_MASK_HSS_TX_CELL_COUNT_STATUS_XFERI 0x40
#define DPX_MASK_HSS_TX_CELL_COUNT_STATUS_XFERE 0x80
/* define bit mask for INDIRECT_CHANNEL_SELECT register (0x68 and 0x70) */
/** Bit 0-3: 4 bits of channel number **/
#define DPX_MASK_IND_CHNL_SELECT_CHANS 0x0F
#define DPX_MASK_IND_CHNL_SELECT_CBUSY 0x80
#define DPX_MASK_IND_CHNL_SELECT_CRWB 0x40
#define DPX_MASK_IND_CHNL_SELECT_DRHCSE 0x20
/* define bit mask for INDIRECT_CHANNEL Configuration register (0x69) */
/** Bit 1: cell delineation and header error detection **/
/** Bit 2: polynomial added to HCS octet **/
/** Bit 3: payload descramling enable/disable **/
/** Bit 4: idle cell filter **/
/** Bit 5: unassigned cell filter **/
/** Bit 6: HCS error filter **/
/** Bit 7: Provision enable bit **/
#define DPX_MASK_IND_CHNL_CFG_DDELIN 0x02
#define DPX_MASK_IND_CHNL_CFG_DHCSADD 0x04
#define DPX_MASK_IND_CHNL_CFG_DDSCR 0x08
#define DPX_MASK_IND_CHNL_CFG_IDLEPASS 0x10
#define DPX_MASK_IND_CHNL_CFG_UNASSPASS 0x20
#define DPX_MASK_IND_CHNL_CFG_HCSPASS 0x40
#define DPX_MASK_IND_CHNL_CFG_PROV 0x80
/* bit mask for Rx Serial Indirect Channel Interrupt Enables register (0x6A) */
#define DPX_MASK_RCV_SER_IND_CHNL_INT_EN_LCDE 0x01
#define DPX_MASK_RCV_SER_IND_CHNL_INT_EN_FOVRE 0x02
#define DPX_MASK_RCV_SER_IND_CHNL_INT_EN_HCSE 0x04
#define DPX_MASK_RCV_SER_IND_CHNL_INT_EN_OOCDE 0x08
/* bit mask for Rx Serial Indirect Channel InterruptStatus register (0x6B) */
/** Bit 0: loss of cell delineation **/
/** Bit 1: FIFO overrun **/
/** Bit 2: HCS error **/
/** Bit 3: enter/exit the SYNC state **/
/** Bit 6: Out of cell delineation persisted **/
/** Bit 7: currently not in SYNC **/
#define DPX_MASK_RCV_SER_IND_CHNL_INT_STATUS_LCDI 0x01
#define DPX_MASK_RCV_SER_IND_CHNL_INT_STATUS_FOVRI 0x02
#define DPX_MASK_RCV_SER_IND_CHNL_INT_STATUS_HCSI 0x04
#define DPX_MASK_RCV_SER_IND_CHNL_INT_STATUS_OOCDI 0x08
#define DPX_MASK_RCV_SER_IND_CHNL_INT_STATUS_LCDV 0x40
#define DPX_MASK_RCV_SER_IND_CHNL_INT_STATUS_OOCDV 0x80
/* define bit mask for Tx INDIRECT_CHANNEL Data register (0x71) */
/** Bit 5: scramble disable **/
/** Bit 6: header scramble enable **/
/** Bit 7: Disable Header Check Sequence (HCS) control insertion **/
/** of the HCS in the fifth byte of the cell **/
#define DPX_MASK_TX_IND_CHNL_DATA_DSCR 0x20
#define DPX_MASK_TX_IND_CHNL_DATA_HSCR 0x40
#define DPX_MASK_TX_IND_CHNL_DATA_DHCS 0x80
/* define bit mask for Master Test register (0x80) */
#define DPX_MASK_MASTER_TEST_HIZIO 0x01
#define DPX_MASK_MASTER_TEST_HIZDATA 0x02
#define DPX_MASK_MASTER_TEST_IOTST 0x04
#define DPX_MASK_MASTER_TEST_DBCTRL 0x08
#define DPX_MASK_MASTER_TEST_PMCTST 0x10
#define DPX_MASK_MASTER_TEST_PMCATST 0x20
#define DPX_MASK_MASTER_TEST_RESERVED 0x40
/* define bit mask for Miscellaneous Test register (0x83) */
#define DPX_MASK_MISC_TEST_CLKSEL_BITS 0x07 /* bits 0,1,2 */
#define DPX_MASK_MISC_TEST_SELOCD 0x08
#define DPX_MASK_MISC_TEST_LINKSELBP 0x10
#define DPX_MASK_MISC_TEST_TCADIS 0x20
/* define for Prepend length */
#define DPX_PRELEN_NO_WORD 0
#define DPX_PRELEN_ONE_WORD 1
#define DPX_PRELEN_TWO_WORD 2
/* define for length of User Header field */
#define DPX_USER_HEADER_4BYTES 0
#define DPX_USER_HEADER_5BYTES 1
#define DPX_USER_HEADER_6BYTES 2
#define DPX_USER_HEADER_RESERVED 3
/*----------------------------------------------------------------------------*/
/* Macro: mDPX_DELAY_LOOP */
/* */
/* Description: Low-level macro that can be used for short time delays, */
/* it depends on the clock speed of the microprocessor. */
/* */
/* Inputs: Delay - number of times to loop to do a NO OP */
/* */
/* Return Codes value read from the address location */
/* */
/*----------------------------------------------------------------------------*/
#define mDPX_DELAY_LOOP(Delay) { volatile int i; for(i=0; i< Delay; ++i); }
/** dpx.c **/
UINT4 duplexISR(DUPLEX duplex);
VOID duplexDPR(DUPLEX duplex);
VOID pDpxProcMasterIntStatus(sDPX_DDB *psDpxDdb, UINT1 u1MasterINTStatus);
VOID pDpxProcMiscIntStatus(sDPX_DDB *psDpxDdb, UINT1 u1MiscIntStatus);
VOID pDpxProcessRxHssInt(sDPX_DDB *psDpxDdb, UINT1 u1HssLnkId,
UINT1 u1HSSIntStatus, UINT1 u1HSSCellStatus);
VOID pDpxEventNotify(sDPX_DDB *psDpxDdb, eDPX_EVENT_ID eEventId,
UINT1 u1IndRegValue, INT4 len, UINT1 *pSupplement);
VOID pDpxProcessRxBOC(sDPX_DDB *psDpxDdb,UINT1 u1HssLnkId,
UINT1 u1RxBocStatus);
VOID duplexHWReset(UINT4 u4BaseAddr);
VOID duplexResetFifos(UINT4 u4BaseAddr);
VOID duplexHWtoggleMastIntEn(UINT4 u4BaseAddr, UINT1 u1Active);
eDPX_MODE duplexHWDevMode(UINT4 u4BaseAddr);
INT4 dpxRxIndChnlWrite(UINT4 u4BaseAddr, UINT1 u1RegID, UINT1 u1ChannelID,
UINT1 u1Value);
INT4 dpxRxIndChnlRead(UINT4 u4BaseAddr, UINT1 RegID, UINT1 ChannelID,
UINT1 *pu1Value);
INT4 dpxTxIndChnlWrite(UINT4 u4BaseAddr, UINT1 u1RegID, UINT1 u1ChannelID,
UINT1 u1Value);
INT4 dpxTxIndChnlRead(UINT4 u4BaseAddr, UINT1 RegID, UINT1 ChannelID,
UINT1 *pu1Value);
INT4 duplexFindDev(sDPX_DDB *psDpxDdb, UINT1 *pu1DdbIdx);
INT4 duplexFindDevFromBaseAddr(UINT4 u4BaseAddr, DUPLEX *psDpxDdb,
UINT1 *pu1DdbIdx);
INT4 duplexValidateIV(eDPX_MODE eDpxMode, sDPX_INIT_VECTOR *psInitVector);
INT4 duplexHWCfgReg(UINT4 u4BaseAddr, eDPX_MODE eDpxMode,
sDPX_INIT_VECTOR *psInitVector);
VOID duplexCfgIntEn(UINT4 u4BaseAddr, eDPX_MODE eDpxMode,
sDPX_INT_ENBLS *psIntEnRegs);
VOID duplexClearRegBits(UINT4 BaseAddr, UINT1 RegID, UINT1 Mask);
VOID duplexSetRegBits(UINT4 BaseAddr, UINT1 RegID, UINT1 Mask);
VOID duplexToggleRegBits(UINT4 BaseAddr, UINT1 RegID, UINT1 Mask,
eDPX_INT_EN_FLAG flag);
VOID dpxWriteInsCRCAccRegs(UINT4 u4BaseAddr, UINT4 u4CRCValue);
VOID dpxReadInsCRCAccRegs(UINT4 u4BaseAddr, UINT4 *pu4CRCValue);
VOID dpxWriteExtCRCAccRegs(UINT4 u4BaseAddr, UINT4 u4CRCValue);
VOID dpxReadExtCRCAccRegs(UINT4 u4BaseAddr, UINT4 *pu4CRCValue);
VOID dpxReadAllPhyRegs(sDPX_DDB *psDpxDdb,
sDPX_SCI_ANY_PHY_REGS *psSciAnyPhyRegs);
VOID dpxWriteAllPhyRegs(sDPX_DDB *psDpxDdb,
sDPX_SCI_ANY_PHY_REGS *psSciAnyPhyRegs);
INT4 duplexGetSciAnyPhyStatus(DUPLEX duplex, UINT1 *pu1Stat);
INT4 duplexGetMicroCellBufStatus(DUPLEX duplex, UINT1 *pu1BufStat);
INT4 duplexGetExtractFifoStatus(DUPLEX duplex, UINT1 u1HssLnkId,UINT1 *pu1Stat);
INT4 duplexGetLogChnlFifoStatus(DUPLEX duplex, UINT1 u1TxFlg, UINT1 *pu1Stat);
INT4 duplexGetRxHssStatus(DUPLEX duplex, UINT1 u1HssLnkId, UINT1 *pu1Stat);
INT4 duplexGetRxSerChnlStatus(DUPLEX duplex, UINT1 u1ChnlId, UINT1 *pu1Stat);
VOID DpxRamInitFix(UINT4 u4BaseAddr);
VOID DpxLowTxPowerFix(UINT4 u4BaseAddr);
VOID DpxInsertAcell(UINT4 u4BaseAddr, sDPX_CELL_HDR *psCellHdr,
UINT1 *pu1CellPyld);
VOID DpxExtractAcell(UINT4 u4BaseAddr, sDPX_CELL_HDR *psCellHdr,
UINT1 *pu1CellPyld);
#endif
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -