dpx.h

交换机中常用芯片链路复用7350的驱动源代码(vxworks中实现)

/* define bit mask for MISCELLANEOUS INTERRUPT STATUS register (0x03) */
#define DPX_MASK_MISC_INT_STATUS_ROOLI             0x01
#define DPX_MASK_MISC_INT_STATUS_RBOCI             0x02
#define DPX_MASK_MISC_INT_STATUS_RCSDI             0x04
#define DPX_MASK_MISC_INT_STATUS_UPFI              0x08
#define DPX_MASK_MISC_INT_STATUS                   0x0F /* all 4 bits */

/* define bit mask for CLOCK MONITOR register (0x04) */
#define DPX_MASK_CLOCK_MONITOR_IFCLKA              0x01
#define DPX_MASK_CLOCK_MONITOR_OFCLKA              0x02
#define DPX_MASK_CLOCK_MONITOR_REFCLKA             0x04
#define DPX_MASK_CLOCK_MONITOR_ROOLV               0x08
#define DPX_MASK_CLOCK_MONITOR_ROOLE               0x10
#define DPX_MASK_CLOCK_MONITOR_ACTIVE_BITS         0x07 /* low 3 bits */

/* define bit mask for Serial Links Maintenance register (0x05) */
 /** Bit 0: Diagnostic loopback 1 enable           			**/
 /** Bit 1: Diagnostic loopback 2 enable          			**/
 /** Bit 2: Mettalic loopback 1 enable            			**/
 /** Bit 3: Mettalic loopback 2 enable             			**/
 /** Bit 4: Transmit Disable the HSS TXD1+/-       		    **/
 /** Bit 5: Transmit Disable the HSS TXD2+/-        		**/
 /** Bit 6: Disable the auto transmission of a RDI on TXD1	**/
 /** Bit 7: Disable the auto transmission of a RDI on TXD2  **/

#define DPX_MASK_SER_LNK_MNT_DLB1                  0x01
#define DPX_MASK_SER_LNK_MNT_DLB2                  0x02
#define DPX_MASK_SER_LNK_MNT_MLB1                  0x04
#define DPX_MASK_SER_LNK_MNT_MLB2                  0x08
#define DPX_MASK_SER_LNK_MNT_TXDIS1                0x10
#define DPX_MASK_SER_LNK_MNT_TXDIS2                0x20
#define DPX_MASK_SER_LNK_MNT_RDIDIS1               0x40
#define DPX_MASK_SER_LNK_MNT_RDIDIS2               0x80

/* define bit mask for CFG_PINS_STATUS register (0x0B)  */
#define DPX_MASK_CFG_PINS_IMASTERV                 0x01  /* bit 0 */
#define DPX_MASK_CFG_PINS_IANYPHYV                 0x02  /* bit 1 */
#define DPX_MASK_CFG_PINS_IBUS8V                   0x04  /* bit 2 */
#define DPX_MASK_CFG_PINS_OMASTERV                 0x08  /* bit 3 */
#define DPX_MASK_CFG_PINS_OANYPHYV                 0x10  /* bit 4 */
#define DPX_MASK_CFG_PINS_OBUS8V                   0x20  /* bit 5 */
#define DPX_MASK_CFG_PINS_SCIANYV                  0x40	 /* bit 6 */

/* define bit mask for SCI-PHY/ANY_PHY Input Config 1 register (0x0C) */
 /** Bit 0: parity                         **/
 /** Bit 2-3: prepend length:2 bits        **/
 /** Bit 7: H5/UDF octets included         **/
#define DPX_MASK_PHY_INPUT_CFG1_PTYP               0x01 
#define DPX_MASK_PHY_INPUT_CFG1_PRELEN             0x0C                                                      
#define DPX_MASK_PHY_INPUT_CFG1_H5UDF              0x80  
                                                   

/* define bit mask for SCI-PHY/ANY_PHY Input Config 2 register (0x0D) */
 /** Bit 0-4:  Phy device polled: 5 bits    **/
 /** Bit 5: UNI or NNI cell header format   **/
 /** Bit 6: Filter for Physical Layer cell  **/
#define DPX_MASK_PHY_INPUT_CFG2_PHYDEV             0x1F                                                   
#define DPX_MASK_PHY_INPUT_CFG2_NNI                0x20                                            
#define DPX_MASK_PHY_INPUT_CFG2_ENFLTR             0x40  
                                            


/* define bit mask for SCI/Any-PHY input interrupt Enables register (0x0E) */
#define DPX_MASK_PHY_INPUT_INT_EN_PARERRE          0x01
#define DPX_MASK_PHY_INPUT_INT_EN_CELLXFERRE       0x02
#define DPX_MASK_PHY_INPUT_INT_EN_PHYCELLE         0x04

/* define bit mask for SCI-PHY/Any-PHY input interrupt status register (0x0F) */
 /** Bit 0:  parity error                   **/
 /** Bit 1:  invalid SOC sequence           **/
 /** Bit 2:  physical cell xferred          **/
#define DPX_MASK_PHY_INPUT_INT_STATUS_PARERRI      0x01  
#define DPX_MASK_PHY_INPUT_INT_STATUS_CELLXFERRI   0x02                                                      
#define DPX_MASK_PHY_INPUT_INT_STATUS_PHYCELLI     0x04  
#define DPX_MASK_PHY_INPUT_INT_STATUS_BITS         0x07 /* all low 3 bits */                                                    

/* define bit mask for SCI-PHY/Anyt-PHY Output Configuration register (0x14) */
#define DPX_MASK_PHY_OUTPUT_CFG_PTYP               0x01
#define DPX_MASK_PHY_OUTPUT_CFG_PRELEN             0x06 /* 2 bits PRELEN[1:0] */
#define DPX_MASK_PHY_OUTPUT_CFG_H5UDF              0x08
#define DPX_MASK_PHY_OUTPUT_CFG_INADDUDF           0x10
#define DPX_MASK_PHY_OUTPUT_CFG_CELLXFERRE         0x40
#define DPX_MASK_PHY_OUTPUT_CFG_CELLXFERRI         0x80

/* define bit mask for SCI-PHY/Anyt-PHY Output Polling Range register (0x15) */
 /** Bit 0  Phy devices polled: 5 bits **/
#define DPX_MASK_PHY_OUTPUT_POLLING_PHYDEV         0x1F  
                                               


/* define bit mask for RXD1/RXD2 HSS BOC  Enables register (0x18, 0x1A) */
#define DPX_MASK_BOC_RCV_EN_BOCE                   0x01
#define DPX_MASK_BOC_RCV_EN_AVC                    0x02
#define DPX_MASK_BOC_RCV_EN_IDLE                   0x04


/* define bit mask for RXD1/RXD2 HSS BOC  Enables register (0x19, 0x1B) */
 /** Bit 0-5:  BOC[5:0] Rx state       **/
 /** Bit 6: valid BOC detection        **/
 /** Bit 7: valid->idle BOC transition **/
#define DPX_MASK_BOC_RCV_STATUS_BOC                0x3F 
#define DPX_MASK_BOC_RCV_STATUS_BOCI               0x40 
#define DPX_MASK_BOC_RCV_STATUS_IDLEI              0x80   
#define DPX_MASK_BOC_RCV_STATUS_IND_BITS           0xC0 /* top 2 bits */                                                

/* define bit mask for TXD1/TXD2 HSS BOC register (0x1D, 0x1F) */
 /** Bit 0-5:  BOC[5:0] tx             **/
#define DPX_MASK_BOC_TX_BC                         0x3F 

/* define bit mask for Microprocessor Cell Buffer Interrupt register (0x20) */
#define DPX_MASK_MICRO_CELL_BUFF_INT_INSRDYE       0x01
#define DPX_MASK_MICRO_CELL_BUFF_INT_INSOVRE       0x02
#define DPX_MASK_MICRO_CELL_BUFF_INT_EXTRDYE       0x04
#define DPX_MASK_MICRO_CELL_BUFF_INT_EXTCRCERRE    0x08
#define DPX_MASK_MICRO_CELL_BUFF_INT_INSRDYI       0x10
#define DPX_MASK_MICRO_CELL_BUFF_INT_INSOVRI       0x20
#define DPX_MASK_MICRO_CELL_BUFF_INT_EXTRDYI       0x40
#define DPX_MASK_MICRO_CELL_BUFF_INT_EXTCRCERRI    0x80
#define DPX_MASK_MICRO_CELL_BUFF_INT_IND_BITS      0xF0  /* 4 indication bits */

/* define bit mask for Micro Insert FIFO Control (0x21) */
 /** Bit 3: abort a cell write                                           **/
 /** Bit 4:  Insert CRC32 using preset                                   **/
 /** Bit 5: indicate the following cell is the last one of the CPCS-PDU  **/
#define DPX_MASK_MICRO_INSERT_FIFO_CTL_INSRST      0x08 
#define DPX_MASK_MICRO_INSERT_FIFO_CTL_INSCRCPR    0x10                                               
#define DPX_MASK_MICRO_INSERT_FIFO_CTL_INSCRCEND   0x20  
                                                

/* define bit mask for Micro Extract FIFO Control (0x22) */
 /** Bit 0: select Rxd1/Rxd2 FIFO                  **/
 /** Bit 3:  abort cell reading                    **/
 /** Bit 4: Extract CRC32 using preset             **/
 /** Bit 5:  enable CRC field check                **/
#define DPX_MASK_MICRO_EXTRACT_FIFO_EXTFSEL        0x01                                                     
#define DPX_MASK_MICRO_EXTRACT_FIFO_EXTABRT        0x08                                                         
#define DPX_MASK_MICRO_EXTRACT_FIFO_EXTCRCPR       0x10                                                 
#define DPX_MASK_MICRO_EXTRACT_FIFO_EXTCRCCHK      0x20 
                                                   

/* define bit mask for Micro Insert FIFO Ready (0x23) */
 /** Bit 0: Insert FIFO is ready to accepy a cell   **/
#define DPX_MASK_MICRO_INSERT_FIFO_INSRDY          0x01 
                                     

/* define bit mask for Micro Extrct FIFO Ready (0x24) */
 /** Bit 0: RXD1 Extract FIFO contains cells  **/
 /** Bit 1: RXD2 Extract FIFO contains cells  **/
#define DPX_MASK_MICRO_EXTRACT_FIFO_EXTRDY0        0x01                                         
#define DPX_MASK_MICRO_EXTRACT_FIFO_EXTRDY1        0x02 
                                         

/* define bit mask for Micro RXD1/RxD2 Extrct FIFO Control (0x30, 0x34) */
 /** Bit 0:  reset Cell Extract FIFO          **/
 /** Bit 1:  enable Extract FIFO overflow int **/
#define DPX_MASK_MICRO_EXTRACT_FIFO_UPFRST         0x01                                                  
#define DPX_MASK_MICRO_EXTRACT_FIFO_UPFOVRE        0x02  
                                          

/* define bit mask for RXD1/RxD2 Extract FIFO Interrupt Status (0x31, 0x35) */
 /** Bit 0: Cell Extract FIFO overflow indication  **/
#define DPX_MASK_MICRO_EXTRACT_FIFO_UPFOVRI        0x01 
                                     


/* bit mask for Rx/Tx Logical Channel FIFO Control registers(0x3C,0x5C) */
 /** Bit 0: reset logical channael FIFOs                        **/
 /** Bit 1: logical channael FIFO overflow interrupt Enable     **/
#define DPX_MASK_LC_FIFO_CTL_FIFORST               0x01                                                  
#define DPX_MASK_LC_FIFO_CTL_FOVRE                 0x02

/* define bit mask for Rx/Tx Logical Channel FIFO Interrupt Status registers 
   (0x3D, 0x5D) */
 /** Bit 0: logical channel FIFO overflow          **/
#define DPX_MASK_LC_FIFO_INT_STATUS_FOVRI          0x01 
                                              

/* define bit mask for RXD1/RXD2 HSS Configuration register (0x40, 0x50) */
 /** Bit 0-1:  User Header length expected         **/
 /** Bit 2: User prepend expected                  **/
 /** Bit 3:  CRC-8 protected: first user perpend   **/
 /** Bit 4:  HCS Error count contains CRC-8 error  **/
 /** Bit 5: Unused                                 **/
 /** Bit 6: Header Descramble enable               **/
 /** Bit 7:  Disable Descramble                    **/
#define DPX_MASK_HSS_RX_CFG_USRHDR                 0x03                                                
#define DPX_MASK_HSS_RX_CFG_PREPEND                0x04                                                      
#define DPX_MASK_HSS_RX_CFG_CELLCRC                0x08                                         
#define DPX_MASK_HSS_RX_CFG_CNTCELLERR             0x10                                      
#define DPX_MASK_HSS_RX_CFG_HDSCR                  0x40                                                   
#define DPX_MASK_HSS_RX_CFG_DDSCR                  0x80 

/* define bit mask for RXD1/RXD2 HSS Cell Filtering Config/Status register 
   (0x41, 0x51) */
 /** Bit 0:  Loss of Signal state                  **/
 /** Bit 1:  Loss of Cell Delineation              **/
 /** Bit 2:  Active bit in cell prepend            **/
 /** Bit 3:  SYNC or "Hunt/PreSync" state          **/
 /** Bit 4:  cells with HCS error passed/droped    **/
#define DPX_MASK_HSS_CELL_FLT_LOSV                 0x01                                                        
#define DPX_MASK_HSS_CELL_FLT_LCDV                 0x02                                                    
#define DPX_MASK_HSS_CELL_FLT_ACTV                 0x04                                                   
#define DPX_MASK_HSS_CELL_FLT_OCDV                 0x10                                               
#define DPX_MASK_HSS_CELL_FLT_HCSPASS              0x40 
                                          

/* define bit mask for RXD1/RXD2 HSS Interrupt Enables register (0x42, 0x52) */
#define DPX_MASK_HSS_INT_EN_LOSE                   0x01
#define DPX_MASK_HSS_INT_EN_LCDE                   0x02
#define DPX_MASK_HSS_INT_EN_ACTE                   0x04
#define DPX_MASK_HSS_INT_EN_CELLERRE               0x08
#define DPX_MASK_HSS_INT_EN_OCDE                   0x10
#define DPX_MASK_HSS_INT_EN_XFERE                  0x20
#define DPX_MASK_HSS_INT_EN_HCSE                   0x40