dpx.h

交换机中常用芯片链路复用7350的驱动源代码(vxworks中实现)

/******************************************************************************/
/**  COPYRIGHT (C) 1999 PMC-SIERRA, INC. ALL RIGHTS RESERVED.                **/
/**--------------------------------------------------------------------------**/
/** This software embodies materials and concepts which are proprietary and  **/
/** confidential to PMC-Sierra, Inc.                                         **/
/** PMC-Sierra distributes this software to its customers pursuant to the    **/ 
/** terms and conditions of the Device Driver Software License Agreement     **/ 
/** contained in the text file software.lic that is distributed along with   **/ 
/** the device driver software. This software can only be utilized if all    **/ 
/** terms and conditions of the Device Driver Software License Agreement are **/ 
/** accepted. If there are any questions, concerns, or if the Device Driver  **/
/** Software License Agreement text file, software.lic, is missing please    **/
/** contact PMC-Sierra for assistance.                                       **/
/**--------------------------------------------------------------------------**/
/**                                                                          **/
/******************************************************************************/
/*******************************************************************************
**    MODULE     : Duplex device drivers header file related to dpx.c
**
**    FILE       : Dpx.h
**      
**    DESCRIPTION: This file contains constants and definitions for DUPLEX 
**                 registers address,bit mask, and prototype for dpx.c
**
**
**    NOTES      :
**
*******************************************************************************/
/* 
**    MODIFICATION HISTORY:
**
** $Log: dpx.h.rca $
** 
**  Revision: 1.1 Wed Aug 16 16:22:10 2000 bhalwani
**    Beta-1.0
**
** 
**  6   06/15/00    Bhalwani        Vortex chipset driver beta-1.0
**  5   06/15/00    Bhalwani        Vortex chipset driver Alpha-1.30
**  4   04/07/00    chenkemi        added FIFO reset
**  3   03/01/00    chenkemi        corrected error in DPX_MASK_HSS_RX_CFG_HDSCR and 
**                                  DPX_MASK_HSS_RX_CFG_DDSCR definition
**  2   01/13/00    chenkemi        alpha-001
**  1   07/02/99    chenkemi        Initial Version
**
**  18  04/07/00    chenkemi        added FIFO reset routine
**  17  03/01/00    chenkemi        corrected DPX_MASK_HSS_RX_CFG_HDSCR and 
**                                  DPX_MASK_HSS_RX_CFG_DDSCR definition
**  16  01/13/00    chenkemi        added Rev.B ID definition
**  15  07/02/99    chenkemi        Beta-1.0
**  14  07/02/99    chenkemi        renamed DUPLEX_DEV_ID
**  13  06/28/99    chenkemi        added function prototypes for Rev.A bug fix.
**  12  06/16/99    chenkemi        fixed DPX_MASK_MICRO_INSERT_FIFO_CTL_INSRST
**  11  06/11/99    chenkemi        fixed EXTABRT bit mask .
**  10  05/28/99    chenkemi        added "pDpxProcMasterIntStatus" and 
**                                  "pDpxProcMiscIntStatus" functions.
**  9   05/25/99    chenkemi        code cleanup after code review
**  8   04/14/99    chenkemi        changed define number for DPX_IND_CHNL_TIMEOUT
**  7   04/12/99    chenkemi        added access timeout error code  for "indirect serial 
**                                  channel"  registers.
**  6   04/08/99    chenkemi        reorganized the file to fit the length limit
**  5   03/31/99    chenkemi        fixed DPX_MASK_PHY_INPUT_INT_STATUS_PHYCELLI definition
**  4   03/29/99    chenkemi        re-organize the header file and added Semaphore 
**                                  definition.
**  3   03/12/99    chenkemi        Version Alpha1.1
**  2   03/09/99    chenkemi        added bit mask and prototype
**  1   03/02/99    chenkemi        Initial Version
**
*/



#ifndef _DPX_H
#define _DPX_H


/** DUPLEX DEVICE ID and TYPE revision **/
#define DUPLEX_DEV_TYPE                 0x01
#define DUPLEX_DEV_ID_REV_A             0x00
#define DUPLEX_DEV_ID_REV_B             0x01

/* DUPLEX Maximum register range */
#define DUPLEX_MAX_REG_ADDR             0x00FF

/* DUPLEX maximum serial indirect channel number */
#define DPX_MAX_SER_IND_CHANNEL_NUMBER  15

/* DUPLEX timeout for indirect channel access loops */
#define DPX_IND_CHNL_TIMEOUT            0x100 


/* define for DUPLEX memory mapped register address offset */
#define DPX_REG_MASTER_RESET_ID                    0x00
#define DPX_REG_MASTER_CFG                         0X01
#define DPX_REG_MASTER_INT_STATUS                  0X02
#define DPX_REG_MISC_INT_STATUS                    0X03
#define DPX_REG_CLOCK_MONITOR                      0X04
#define DPX_REG_SER_LNK_MNT                        0X05
#define DPX_REG_EXT_ADDR_MATCH_LSB                 0X06
#define DPX_REG_EXT_ADDR_MATCH_MSB                 0x07
#define DPX_REG_EXT_ADDR_MASK_LSB	               0x08
#define DPX_REG_EXT_ADDR_MASK_MSB                  0x09
#define DPX_REG_OUTPUT_ADDR_MATCH	               0x0A
#define DPX_REG_CFG_PINS_STATUS                    0x0B
#define DPX_REG_PHY_INPUT_CFG1                     0x0C
#define DPX_REG_PHY_INPUT_CFG2                     0x0D
#define DPX_REG_PHY_INPUT_INT_EN                   0x0E
#define DPX_REG_PHY_INPUT_INT_STATUS               0x0F
#define DPX_REG_INPUT_CELL_AV_EN_LSB               0x10
#define DPX_REG_INPUT_CELL_AV_EN_2ND               0x11
#define DPX_REG_INPUT_CELL_AV_EN_3RD               0x12
#define DPX_REG_INPUT_CELL_AV_EN_MSB               0x13
#define DPX_REG_PHY_OUTPUT_CFG                     0x14
#define DPX_REG_PHY_OUTPUT_POLL_RANGE              0x15

#define DPX_REG_RXD1_BOC_RCV_EN                    0x18
#define DPX_REG_RXD1_BOC_STATUS                    0x19
#define DPX_REG_RXD2_BOC_RCV_EN                    0x1A
#define DPX_REG_RXD2_BOC_STATUS                    0x1B

#define DPX_REG_TXD1_BOC                           0x1D
#define DPX_REG_TXD2_BOC                           0x1F
#define DPX_REG_MICRO_CELL_BUFF_INT                0x20
#define DPX_REG_MICRO_INSERT_FIFO_CTL              0x21
#define DPX_REG_MICRO_EXTRACT_FIFO_CTL             0x22
#define DPX_REG_MICRO_INSERT_FIFO_RDY              0x23
#define DPX_REG_MICRO_EXTRACT_FIFO_RDY             0x24
#define DPX_REG_INSERT_CRC_ACC_LSB                 0x25
#define DPX_REG_INSERT_CRC_ACC_2ND                 0x26
#define DPX_REG_INSERT_CRC_ACC_3RD                 0x27
#define DPX_REG_INSERT_CRC_ACC_MSB                 0x28
#define DPX_REG_EXTRACT_CRC_ACC_LSB                0x29
#define DPX_REG_EXTRACT_CRC_ACC_2ND                0x2A
#define DPX_REG_EXTRACT_CRC_ACC_3RD                0x2B
#define DPX_REG_EXTRACT_CRC_ACC_MSB                0x2C
#define DPX_REG_MICRO_CELL_BUFF_DATA               0x2D

#define DPX_REG_RXD1_EFIFO_CTL                     0x30
#define DPX_REG_RXD1_EFIFO_INT_STATUS              0x31

#define DPX_REG_RXD2_EFIFO_CTL                     0x34
#define DPX_REG_RXD2_EFIFO_INT_STATUS              0x35

#define DPX_REG_RCV_LC_FIFO_CTL                    0x3C
#define DPX_REG_RCV_LC_FIFO_INT_STATUS             0x3D

#define DPX_REG_RXD1_HSS_CFG                       0x40
#define DPX_REG_RXD1_HSS_CELL_FILT_CFG_STATUS      0x41
#define DPX_REG_RXD1_HSS_INT_EN                    0x42
#define DPX_REG_RXD1_HSS_INT_STATUS                0x43
#define DPX_REG_RXD1_HSS_HCS_ERR_COUNT             0x44
#define DPX_REG_RXD1_HSS_CELL_COUNT_LSB            0x45
#define DPX_REG_RXD1_HSS_CELL_COUNT_2ND            0x46
#define DPX_REG_RXD1_HSS_CELL_COUNT_MSB            0x47

#define DPX_REG_RXD2_HSS_CFG                       0x50
#define DPX_REG_RXD2_HSS_CELL_FILT_CFG_STATUS      0x51
#define DPX_REG_RXD2_HSS_INT_EN                    0x52
#define DPX_REG_RXD2_HSS_INT_STATUS                0x53
#define DPX_REG_RXD2_HSS_HCS_ERR_COUNT             0x54
#define DPX_REG_RXD2_HSS_CELL_COUNT_LSB            0x55
#define DPX_REG_RXD2_HSS_CELL_COUNT_2ND            0x56
#define DPX_REG_RXD2_HSS_CELL_COUNT_MSB            0x57

#define DPX_REG_TX_LC_FIFO_CTL                     0x5C
#define DPX_REG_TX_LC_FIFO_INT_STATUS              0x5D
#define DPX_REG_TX_LC_FIFO_DEPTH                   0x5E
#define DPX_REG_TX_LC_FIFO_READY                   0x5F

#define DPX_REG_TX_HSS_CFG                         0x60
#define DPX_REG_TX_HSS_CELL_COUNT_STATUS           0x61
#define DPX_REG_TX_HSS_CELL_COUNT_LSB              0x62
#define DPX_REG_TX_HSS_CELL_COUNT_2ND              0x63
#define DPX_REG_TX_HSS_CELL_COUNT_MSB              0x64

#define DPX_REG_RCV_SER_IND_CHNL_SELECT            0x68
#define DPX_REG_RCV_SER_IND_CHNL_CFG               0x69
#define DPX_REG_RCV_SER_IND_CHNL_INT_EN            0x6A
#define DPX_REG_RCV_SER_IND_CHNL_INT_STATUS        0x6B
#define DPX_REG_RCV_SER_IND_CHNL_HCS_ERR_COUNT     0x6C
#define DPX_REG_RCV_SER_LCD_COUNT_THRESHOLD        0x6D

#define DPX_REG_TX_SER_IND_CHNL_SELECT             0x70
#define DPX_REG_TX_SER_IND_CHNL_DATA               0x71

#define DPX_REG_TX_SER_FRAM_BIT_THRESHOLD          0x74

/* Test Mode Register */
#define DPX_REG_MASTER_TEST                        0x80
#define DPX_REG_MISC_TEST                          0x83


/* define bit mask for MASTER RESET and ID register (0x00) */
#define DPX_MASK_MASTER_ID                         0x0F
#define DPX_MASK_MASTER_TYPE                       0x70

/* define bit mask for MASTER CONFIGURATION register (0x01) */
#define DPX_MASK_MASTER_CFG_ACTIVE                 0x01
#define DPX_MASK_MASTER_CFG_RXAUTOSEL              0x02
#define DPX_MASK_MASTER_CFG_MINTE                  0x04
#define DPX_MASK_MASTER_CFG_RESETO                 0x08
#define DPX_MASK_MASTER_CFG_LXRCINV                0x10
#define DPX_MASK_MASTER_CFG_LXTCINV                0x20

/* define bit mask for MASTER INTERRUPT STATUS register (0x02) */
#define DPX_MASK_MASTER_INT_STATUS_RX1I            0x01
#define DPX_MASK_MASTER_INT_STATUS_RX2I            0x02
#define DPX_MASK_MASTER_INT_STATUS_TXI             0x04
#define DPX_MASK_MASTER_INT_STATUS_RFI             0x08
#define DPX_MASK_MASTER_INT_STATUS_TFI             0x10
#define DPX_MASK_MASTER_INT_STATUS_ICIFI           0x20
#define DPX_MASK_MASTER_INT_STATUS_OCIFI           0x40
#define DPX_MASK_MASTER_INT_STATUS_UPCIFI          0x80