📄 dpx_api.h
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DPX_EVENT_PHY_OUTPUT_ERROR, /* register 0x14, bit 7 */
DPX_EVENT_MICRO_INSERT_FIFO_READY, /* register 0x20, bit 4 */
DPX_EVENT_MICRO_INSERT_FIFO_FULL, /* register 0x20, bit 5 */
DPX_EVENT_EXTRACT_CELL_CRC_ERROR, /* register 0x20, bit 7 */
DPX_EVENT_CLOCK_LOCK_FAIL, /* register 0x04, bit 3 */
/* Type 2 events: For channel 0 to 15 */
DPX_EVENT_RX_SER_CHNL_OUT_OF_DELIN, /* register 0x6B, bits 0,6 */
DPX_EVENT_RX_SER_CHNL_IN_DELIN, /* register 0x6B, bits 0,6 */
DPX_EVENT_RX_SER_CHNL_FIFO_OVERFLOW, /* register 0x6B, bit 1 */
DPX_EVENT_RX_SER_CHNL_HCS_ERROR, /* register 0x6B, bit 2 */
DPX_EVENT_RX_SER_CHNL_OUT_OF_SYNC, /* register 0x6B, bits 3,7 */
DPX_EVENT_RX_SER_CHNL_IN_SYNC, /* register 0x6B, bits 3,7 */
/* Type 3 events: For RXD1 and RXD2 */
DPX_EVENT_RX_EXTRACT_FIFO_OVERFLOW, /* registers 0x31, 0x35, bit 0 */
DPX_EVENT_RX_HSS_LOSS_OF_SIGNAL, /* registers 0x43, 0x53, bit 0 */
/* registers 0x41, 0x51, bit 0 */
DPX_EVENT_RX_HSS_SIGNAL_DETECTED, /* registers 0x43, 0x53, bit 0 */
/* registers 0x41, 0x51, bit 0 */
DPX_EVENT_RX_HSS_OUT_OF_DELIN, /* registers 0x43, 0x53, bit 1 */
/* registers 0x41, 0x51, bit 1 */
DPX_EVENT_RX_HSS_IN_DELIN, /* registers 0x43, 0x53, bit 1 */
/* registers 0x41, 0x51, bit 1 */
DPX_EVENT_RX_HSS_ACTIVE_BIT, /* registers 0x43, 0x53, bit 2 */
/* registers 0x41, 0x51, bit 2 */
DPX_EVENT_RX_HSS_NO_ACTIVE_BIT, /* registers 0x43, 0x53, bit 2 */
/* registers 0x41, 0x51, bit 2 */
DPX_EVENT_RX_HSS_OUT_OF_SYNC, /* registers 0x43, 0x53, bit 4 */
/* registers 0x41, 0x51, bit 4 */
DPX_EVENT_RX_HSS_IN_SYNC, /* registers 0x43, 0x53, bit 4 */
/* registers 0x41, 0x51, bit 4 */
DPX_EVENT_RX_HSS_CRC8_ERROR, /* registers 0x43, 0x53, bit 3 */
DPX_EVENT_RX_HSS_HCS_ERROR, /* registers 0x43, 0x53, bit 5 */
DPX_EVENT_RX_HSS_COUNT_UPDATED, /* registers 0x43, 0x53, bit 6 */
DPX_EVENT_RX_HSS_COUNT_OVERFLOW, /* registers 0x43, 0x53, bit 7 */
DPX_EVENT_RX_BOC, /* registers 0x19, 0x1B, bit 6 */
DPX_EVENT_EXTRACT_CELL /* registers 0x20, bit 6 */
} eDPX_EVENT_ID;
/* Duplex statistical counts for events */
typedef struct _dpx_Stat_Counts
{
/* Type 1 events: no index */
UINT4 Count_Tx_Hss_Count_Overflow; /* register 0x61, bit 5 */
UINT4 Count_Tx_Hss_Count_Updated; /* register 0x61, bit 6 */
UINT4 Count_Rx_Lc_Fifo_Overflow; /* register 0x3D, bit 0 */
UINT4 Count_Tx_Lc_Fifo_Overflow; /* register 0x5D, bit 0 */
UINT4 Count_Phy_Input_Cell_Xfered; /* register 0x0F, bit 2 */
UINT4 Count_Invalid_SOC_Sequence; /* register 0x0F, bit 1 */
UINT4 Count_Phy_Input_Parity; /* register 0x0F, bit 0 */
UINT4 Count_Phy_Output_Error; /* register 0x14, bit 7 */
UINT4 Count_Micro_Insert_Fifo_Ready; /* register 0x20, bit 4 */
UINT4 Count_Micro_Insert_Fifo_Full; /* register 0x20, bit 5 */
UINT4 Count_Extract_Cell_CRC_Error; /* register 0x20, bit 7 */
UINT4 Count_Clock_Lock_Fail; /* register 0x04, bit 3 */
/* Type 2 events: indexed by Channel Id */
UINT4 Count_RxSerChnl_Out_Of_Delin[16]; /* register 0x6B, bits 0,6 */
UINT4 Count_RxSerChnl_In_Delin[16]; /* register 0x6B, bits 0,6 */
UINT4 Count_RxSerChnl_Fifo_Overflow[16]; /* register 0x6B, bit 1 */
UINT4 Count_RxSerChnl_HCS_Error[16]; /* register 0x6B, bit 2 */
UINT4 Count_RxSerChnl_Out_Of_Sync[16]; /* register 0x6B, bits 3,7 */
UINT4 Count_RxSerChnl_in_Sync[16]; /* register 0x6B, bits 3,7 */
/* Type 3 events: indexed by HSS Link Id */
UINT4 Count_RxHss_Extract_Fifo_Overflow[2];
/* registers 0x31, 0x35, bit 0 */
UINT4 Count_RxHss_Loss_Of_Signal[2]; /* registers 0x43, 0x53, bit 0 */
/* registers 0x41, 0x51, bit 0 */
UINT4 Count_RxHss_Signal_Detected[2];/* registers 0x43, 0x53, bit 0 */
/* registers 0x41, 0x51, bit 0 */
UINT4 Count_RxHss_Out_Of_Delin[2]; /* registers 0x43, 0x53, bit 1 */
/* registers 0x41, 0x51, bit 1 */
UINT4 Count_RxHss_In_Delin[2]; /* registers 0x43, 0x53, bit 1 */
/* registers 0x41, 0x51, bit 1 */
UINT4 Count_RxHss_Active_Bit[2]; /* registers 0x43, 0x53, bit 2 */
/* registers 0x41, 0x51, bit 2 */
UINT4 Count_RxHss_No_Active_Bit[2]; /* registers 0x43, 0x53, bit 2 */
/* registers 0x41, 0x51, bit 2 */
UINT4 Count_RxHss_Out_Of_Sync[2]; /* registers 0x43, 0x53, bit 4 */
/* registers 0x41, 0x51, bit 4 */
UINT4 Count_RxHss_In_Sync[2]; /* registers 0x43, 0x53, bit 4 */
/* registers 0x41, 0x51, bit 4 */
UINT4 Count_RxHss_CRC8_Error[2]; /* registers 0x43, 0x53, bit 3 */
UINT4 Count_RxHss_HCS_Error[2]; /* registers 0x43, 0x53, bit 5 */
UINT4 Count_RxHss_Count_Updated[2]; /* registers 0x43, 0x53, bit 6 */
UINT4 Count_RxHss_Count_Overflow[2]; /* registers 0x43, 0x53, bit 7 */
UINT4 Count_Rx_BOCs[2]; /* registers 0x19, 0x1B, bit 6 */
/* others */
UINT4 Count_Extract_Cells; /* registers 0x20, bit 6 */
UINT4 Count_Interrupts; /* number of interrupts */
} sDPX_STAT_COUNTS;
/* Duplex Rx BOC Indication structure */
typedef struct _dpx_Rx_BOC_Ind
{
UINT1 u1HssLnkId;
UINT1 u1BOC;
UINT1 u1IndRegValue;
} sDPX_RX_BOC_IND;
/* Duplex event Notify indication */
typedef struct _dpx_Event_Notify_Ind
{
eDPX_EVENT_ID eEventId;
UINT1 u1IndRegValue;
UINT1 supplement[DPX_MAX_IND_BUFSZ-sizeof(eDPX_EVENT_ID)-1];
} sDPX_EVENT_NOTIFY_IND;
/* function pointer prototypes for callback functions */
/*----------------------------------------------------*/
typedef VOID (*DPX_IND_CB_FN)(DPX_USR_CTXT usr_ctxt, sDPX_IND_BUF *pIndBuf);
typedef UINT1 (*DPX_CELLTYPE_FN)(UINT1 *pu1Hdr, UINT4 *pu4Crc32Prev);
/* Initialization Vector passed in from user */
typedef struct _dpx_Init_Vector
{
sDPX_REGS sRegInfo;
DPX_IND_CB_FN indNotify;
DPX_IND_CB_FN indRxBOC;
DPX_IND_CB_FN indRxCell;
DPX_CELLTYPE_FN pCellTypeFn;
UINT4 u4Reserved;
} sDPX_INIT_VECTOR;
/* Device Data Block */
typedef struct _dpxDdb
{
DPX_USR_CTXT usrCtxt;
void *pSysInfo;
UINT4 u4BaseAddr;
eDPX_MODE eDevMode;
eDPX_STATE eDevState;
UINT1 u1IntrProcEn;
sDPX_INIT_VECTOR sInitVector;
sDPX_INT_ENBLS sIntEnbls;
DPX_IND_CB_FN indNotify;
DPX_IND_CB_FN indRxBOC;
DPX_IND_CB_FN indRxCell;
DPX_CELLTYPE_FN pCellTypeFn;
sDPX_STAT_COUNTS sStatCounts;
DPX_SEM_ID lockId; /* Semaphore ID for the structure data */
UINT4 u4Reserved;
}sDPX_DDB;
/* Global Driver Database (GDD) */
typedef struct _dpxGdd
{
UINT1 u1NumDevs; /* number of devices added */
sDPX_DDB *pDdb[DPX_MAX_NUM_DEVS];
/* array of pointers to the individual DDBs */
UINT4 u4Reserved ; /* reserved */
}sDPX_GDD;
/* HSS Counts */
typedef struct _dpx_hss_Cnts
{
UINT4 u4RxCells[2];
UINT4 u4TxCells;
UINT1 u1HcsErrs[2];
} sDPX_HSS_CNTS;
/* define bit mask for Cell Type in sDPX_CELL_CTRL structure */
#define DPX_CELL_TYPE_CRC 0x01
#define DPX_CELL_TYPE_FIRST_CELL 0x02
#define DPX_CELL_TYPE_LAST_CELL 0x04
#define DPX_CELL_TYPE_DISCARD 0x08
/* defines for duplex Loopback flag */
#define DPX_LPBK_RESET 0
#define DPX_LPBK_SET 1
/* defines for Loopback type */
#define DPX_DIAG_LPBK 0
#define DPX_LINE_LPBK 1
/* defines for HSS link ID */
#define DPX_RXD1 0
#define DPX_RXD2 1
/* DUPLEX function prototypes */
/*--------- dpx_api.c ----------------*/
INT4 duplexModuleInit(VOID);
VOID duplexModuleShutdown(VOID);
INT4 duplexAdd(DPX_USR_CTXT usrCtxt, DUPLEX *pDuplex);
INT4 duplexDelete(DUPLEX Duplex);
INT4 duplexRead(DUPLEX duplex, UINT2 u2RegId, UINT1 *pu1Val);
INT4 duplexWrite(DUPLEX duplex, UINT2 u2RegId, UINT1 u1Val);
INT4 duplexInit(DUPLEX duplex, sDPX_INIT_VECTOR sInitVector);
INT4 duplexReset(DUPLEX duplex);
INT4 duplexInstallIndFn(DUPLEX duplex, eDPX_CB_TYPE eCbType,
DPX_IND_CB_FN pCbFn);
INT4 duplexRemoveIndFn(DUPLEX duplex, eDPX_CB_TYPE eCbType);
INT4 duplexActivate(DUPLEX duplex);
INT4 duplexDeactivate(DUPLEX duplex);
INT4 duplexRegisterTest(DUPLEX duplex);
INT4 duplexLoopback(DUPLEX duplex, UINT1 u1HssLnkId, UINT1 u1LpbkType,
UINT1 u1Enable);
INT4 duplexRemoteReset(DUPLEX duplex);
INT4 duplexHssActiveLnkGetCfg(DUPLEX duplex, eHSS_LNK_SEL *peLnkSel);
INT4 duplexHssActiveLnkSetCfg(DUPLEX duplex, eHSS_LNK_SEL eLnkSel);
INT4 duplexHssGetCfg(DUPLEX duplex, eDPX_HSS_REG eHssRegId,
sDPX_HSS_REGS *psHssRegs);
INT4 duplexHssSetCfg(DUPLEX duplex, eDPX_HSS_REG eHssRegId,
sDPX_HSS_REGS *psHssRegs);
INT4 duplexInsertCell(DUPLEX duplex, sDPX_CELL_HDR *psCellHdr,
UINT1 *pu1CellPyld, sDPX_CELL_CTRL *psCtrl);
INT4 duplexExtractCell(DUPLEX duplex, UINT1 u1HssLnkId,sDPX_CELL_HDR *psCellHdr,
UINT1 *pu1CellPyld, sDPX_CELL_CTRL *psCtrl);
INT4 duplexCheckExtractFifos(DUPLEX duplex, UINT1 *pu1CellReady);
INT4 duplexEnableRxCellInd(DUPLEX duplex);
INT4 duplexInstallCellTypeFn(DUPLEX duplex, DPX_CELLTYPE_FN pCellTypeFn);
INT4 duplexTxBOC(DUPLEX duplex, UINT1 u1HssLnkId, UINT1 u1Code);
INT4 duplexRxBOC(DUPLEX duplex, UINT1 u1HssLnkId, UINT1 *pu1Code);
INT4 duplexSetAutoRDITx(DUPLEX duplex, UINT1 u1HssLnkId, UINT1 u1DisableFlge);
INT4 duplexSciAnyPhyGetConfig(DUPLEX duplex,
eDPX_SCI_ANY_PHY_REG eSciAnyPhyRegId,
sDPX_SCI_ANY_PHY_REGS *psSciAnyPhyRegs);
INT4 duplexSciAnyPhySetConfig(DUPLEX duplex,
eDPX_SCI_ANY_PHY_REG eSciAnyPhyRegId,
sDPX_SCI_ANY_PHY_REGS *psSciAnyPhyRegs);
INT4 duplexRxSerChnlReadReg(DUPLEX duplex, UINT1 u1SerChnlId,
eDPX_CLK_SER_REG eClkSerRegId, UINT1 *pu1RegVal);
INT4 duplexRxSerChnlWriteReg(DUPLEX duplex, UINT1 u1SerChnlId,
eDPX_CLK_SER_REG eClkSerRegId, UINT1 u1RegVal);
INT4 duplexTxSerChnlReadReg(DUPLEX duplex, UINT1 u1SerChnlId,
eDPX_CLK_SER_REG eClkSerRegId, UINT1 *pu1RegVal);
INT4 duplexTxSerChnlWriteReg(DUPLEX duplex, UINT1 u1SerChnlId,
eDPX_CLK_SER_REG eClkSerRegId, UINT1 u1RegVal);
INT4 duplexRxSerChnlHCSCntResetEn(DUPLEX duplex, UINT1 u1Enable);
INT4 duplexGetHssLnkRxCounts(DUPLEX duplex, UINT1 u1HssLnkId,
UINT4 *pu4RxCells, UINT4 *pu4HcsErrs );
INT4 duplexGetHssLnkTxCounts(DUPLEX duplex, UINT4 *pu4TxCells );
INT4 duplexGetAllHssCounts(DUPLEX duplex, sDPX_HSS_CNTS *psHssCnts);
INT4 duplexGetRxSerChnlHCSCount(DUPLEX duplex, UINT1 u1ChnlId, UINT1 *pu1Cnt);
INT4 duplexGetClockStatus(DUPLEX duplex, UINT1 *pu1ClkStat);
INT4 duplexGetStatisticCounts(DUPLEX duplex, sDPX_STAT_COUNTS *psStatCounts);
INT4 duplexResetStatisticCounts(DUPLEX duplex);
#endif
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