📄 dm9ks.c
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netif_stop_queue(dev); /* free interrupt */ free_irq(dev->irq, dev); /* RESET devie */ phy_write(db, 0x00, 0x8000); /* PHY RESET */ iow(db, DM9KS_GPR, 0x01); /* Power-Down PHY */ iow(db, DM9KS_IMR, DM9KS_DISINTR); /* Disable all interrupt */ iow(db, DM9KS_RXCR, 0x00); /* Disable RX */ /* Dump Statistic counter */#if FALSE printk("\nRX FIFO OVERFLOW %lx\n", db->stats.rx_fifo_errors); printk("RX CRC %lx\n", db->stats.rx_crc_errors); printk("RX LEN Err %lx\n", db->stats.rx_length_errors); printk("RESET %x\n", db->reset_counter); printk("RESET: TX Timeout %x\n", db->reset_tx_timeout); printk("g_TX_nsr %x\n", g_TX_nsr);#endif return 0;}static void dmfe_tx_done(unsigned long unused){ struct net_device *dev = dmfe_dev; board_info_t *db = (board_info_t *)dev->priv; int nsr; DMFE_DBUG(0, "dmfe_tx_done()", 0); nsr = ior(db, DM9KS_NSR); if(nsr & 0x04) db->tx_pkt_cnt--; if(nsr & 0x08) db->tx_pkt_cnt--; if (db->tx_pkt_cnt < 0) { printk("[dmfe_tx_done] tx_pkt_cnt ERROR!!\n"); db->tx_pkt_cnt =0; } if (db->Speed == 10) {if(db->tx_pkt_cnt < 1 ) netif_wake_queue(dev);} else {if(db->tx_pkt_cnt < 2 ) netif_wake_queue(dev);} return;}/* DM9000 insterrupt handler receive the packet to upper layer, free the transmitted packet*/#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)static void dmfe_interrupt(int irq, void *dev_id, struct pt_regs *regs)#elsestatic irqreturn_t dmfe_interrupt(int irq, void *dev_id, struct pt_regs *regs)#endif{ struct net_device *dev = dev_id; board_info_t *db; int int_status,i; u8 reg_save; DMFE_DBUG(0, "dmfe_interrupt()", 0); /* A real interrupt coming */ db = (board_info_t *)dev->priv; spin_lock(&db->lock); /* Save previous register address */ reg_save = inb(db->io_addr); /* Disable all interrupt */ iow(db, DM9KS_IMR, DM9KS_DISINTR); /* Got DM9000A/DM9010 interrupt status */ int_status = ior(db, DM9KS_ISR); /* Got ISR */ iow(db, DM9KS_ISR, int_status); /* Clear ISR status */ /* Link status change */ if (int_status & DM9KS_LINK_INTR) { netif_stop_queue(dev); for(i=0; i<500; i++) /*wait link OK, waiting time =0.5s */ { phy_read(db,0x1); if(phy_read(db,0x1) & 0x4) /*Link OK*/ { /* wait for detected Speed */ for(i=0; i<200;i++) udelay(1000); /* set media speed */ if(phy_read(db,0)&0x2000) db->Speed =100; else db->Speed =10; break; } udelay(1000); } netif_wake_queue(dev); //printk("[INTR]i=%d speed=%d\n",i, (int)(db->Speed)); } /* Received the coming packet */ if (int_status & DM9KS_RX_INTR) dmfe_packet_receive(dev); /* Trnasmit Interrupt check */ if (int_status & DM9KS_TX_INTR) dmfe_tx_done(0); if (db->cont_rx_pkt_cnt>=CONT_RX_PKT_CNT) { iow(db, DM9KS_IMR, 0xa2); } else { /* Re-enable interrupt mask */ iow(db, DM9KS_IMR, DM9KS_REGFF); } /* Restore previous register address */ outb(reg_save, db->io_addr); spin_unlock(&db->lock); #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) return IRQ_HANDLED;#endif}/* Get statistics from driver.*/static struct net_device_stats * dmfe_get_stats(struct net_device *dev){ board_info_t *db = (board_info_t *)dev->priv; DMFE_DBUG(0, "dmfe_get_stats", 0); return &db->stats;}/* Process the upper socket ioctl command*/static int dmfe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd){ DMFE_DBUG(0, "dmfe_do_ioctl()", 0); return 0;}/* Our watchdog timed out. Called by the networking layer */static voiddmfe_timeout(struct net_device *dev){ board_info_t *db = (board_info_t *)dev->priv; DMFE_DBUG(0, "dmfe_TX_timeout()", 0); printk("TX time-out -- dmfe_timeout().\n"); db->reset_tx_timeout++; db->stats.tx_errors++;#if FALSE printk("TX packet count = %d\n", db->tx_pkt_cnt); printk("TX timeout = %d\n", db->reset_tx_timeout); printk("22H=0x%02x 23H=0x%02x\n",ior(db,0x22),ior(db,0x23)); printk("faH=0x%02x fbH=0x%02x\n",ior(db,0xfa),ior(db,0xfb));#endif dmfe_reset(dev); }static void dmfe_reset(struct net_device * dev){ board_info_t *db = (board_info_t *)dev->priv; u8 reg_save; int i; /* Save previous register address */ reg_save = inb(db->io_addr); netif_stop_queue(dev); db->reset_counter++; dmfe_init_dm9000(dev); db->Speed =10; for(i=0; i<1000; i++) /*wait link OK, waiting time=1 second */ { if(phy_read(db,0x1) & 0x4) /*Link OK*/ { if(phy_read(db,0)&0x2000) db->Speed =100; else db->Speed =10; break; } udelay(1000); } netif_wake_queue(dev); /* Restore previous register address */ outb(reg_save, db->io_addr);}/* A periodic timer routine*/static void dmfe_timer(unsigned long data){ struct net_device * dev = (struct net_device *)data; board_info_t *db = (board_info_t *)dev->priv; DMFE_DBUG(0, "dmfe_timer()", 0); if (db->cont_rx_pkt_cnt>=CONT_RX_PKT_CNT) { db->cont_rx_pkt_cnt=0; iow(db, DM9KS_IMR, DM9KS_REGFF); } /* Set timer again */ db->timer.expires = DMFE_TIMER_WUT; add_timer(&db->timer); return;}#if !defined(CHECKSUM)#define check_rx_ready(a) ((a) == 0x01)#elseinline u8 check_rx_ready(u8 rxbyte){ if (!(rxbyte & 0x01)) return 0; return ((rxbyte >> 4) | 0x01);}#endif/* Received a packet and pass to upper layer*/static void dmfe_packet_receive(struct net_device *dev){ board_info_t *db = (board_info_t *)dev->priv; struct sk_buff *skb; u8 rxbyte, val; u16 i, GoodPacket, tmplen = 0, MDRAH, MDRAL; u32 tmpdata; rx_t rx; u16 * ptr = (u16*)℞ u8* rdptr; DMFE_DBUG(0, "dmfe_packet_receive()", 0); do { /*store the value of Memory Data Read address register*/ MDRAH=ior(db, DM9KS_MDRAH); MDRAL=ior(db, DM9KS_MDRAL); ior(db, DM9KS_MRCMDX); /* Dummy read */ rxbyte = inb(db->io_data); /* Got most updated data */ /* packet ready to receive check */ if(!(val = check_rx_ready(rxbyte))) break; /* A packet ready now & Get status/length */ GoodPacket = TRUE; outb(DM9KS_MRCMD, db->io_addr); /* Read packet status & length */ switch (db->io_mode) { case DM9KS_BYTE_MODE: *ptr = inb(db->io_data) + (inb(db->io_data) << 8); *(ptr+1) = inb(db->io_data) + (inb(db->io_data) << 8); break; case DM9KS_WORD_MODE: *ptr = inw(db->io_data); *(ptr+1) = inw(db->io_data); break; case DM9KS_DWORD_MODE: tmpdata = inl(db->io_data); *ptr = tmpdata; *(ptr+1) = tmpdata >> 16; break; default: break; } /* Packet status check */ if (rx.desc.status & 0xbf) { GoodPacket = FALSE; if (rx.desc.status & 0x01) { db->stats.rx_fifo_errors++; printk("<RX FIFO error>\n"); } if (rx.desc.status & 0x02) { db->stats.rx_crc_errors++; printk("<RX CRC error>\n"); } if (rx.desc.status & 0x80) { db->stats.rx_length_errors++; printk("<RX Length error>\n"); } if (rx.desc.status & 0x08) printk("<Physical Layer error>\n"); } if (!GoodPacket) { // drop this packet!!! switch (db->io_mode) { case DM9KS_BYTE_MODE: for (i=0; i<rx.desc.length; i++) inb(db->io_data); break; case DM9KS_WORD_MODE: tmplen = (rx.desc.length + 1) / 2; for (i = 0; i < tmplen; i++) inw(db->io_data); break; case DM9KS_DWORD_MODE: tmplen = (rx.desc.length + 3) / 4; for (i = 0; i < tmplen; i++) inl(db->io_data); break; } continue;/*next the packet*/ } skb = dev_alloc_skb(rx.desc.length+4); if (skb == NULL ) { printk(KERN_INFO "%s: Memory squeeze.\n", dev->name); /*re-load the value into Memory data read address register*/ iow(db,DM9KS_MDRAH,MDRAH); iow(db,DM9KS_MDRAL,MDRAL); return; } else { /* Move data from DM9000 */ skb->dev = dev; skb_reserve(skb, 2); rdptr = (u8*)skb_put(skb, rx.desc.length - 4); /* Read received packet from RX SARM */ switch (db->io_mode) { case DM9KS_BYTE_MODE: for (i=0; i<rx.desc.length; i++) rdptr[i]=inb(db->io_data); break; case DM9KS_WORD_MODE: tmplen = (rx.desc.length + 1) / 2; for (i = 0; i < tmplen; i++) ((u16 *)rdptr)[i] = inw(db->io_data); break; case DM9KS_DWORD_MODE: tmplen = (rx.desc.length + 3) / 4; for (i = 0; i < tmplen; i++) ((u32 *)rdptr)[i] = inl(db->io_data); break; } /* Pass to upper layer */ skb->protocol = eth_type_trans(skb,dev);#if defined(CHECKSUM) if (val == 0x01) skb->ip_summed = CHECKSUM_UNNECESSARY;#endif netif_rx(skb); dev->last_rx=jiffies; db->stats.rx_packets++; db->stats.rx_bytes += rx.desc.length; db->cont_rx_pkt_cnt++; if (db->cont_rx_pkt_cnt>=CONT_RX_PKT_CNT) { dmfe_tx_done(0); break; } } }while((rxbyte & 0x01) == DM9KS_PKT_RDY); DMFE_DBUG(0, "[END]dmfe_packet_receive()", 0); }/* Read a word data from SROM*/static u16 read_srom_word(board_info_t *db, int offset){ iow(db, DM9KS_EPAR, offset); iow(db, DM9KS_EPCR, 0x4); udelay(200); iow(db, DM9KS_EPCR, 0x0); return (ior(db, DM9KS_EPDRL) + (ior(db, DM9KS_EPDRH) << 8) );}/* Set DM9000A/DM9010 multicast address*/static void dm9000_hash_table(struct net_device *dev){ board_info_t *db = (board_info_t *)dev->priv; struct dev_mc_list *mcptr = dev->mc_list; int mc_cnt = dev->mc_count; u32 hash_val; u16 i, oft, hash_table[4]; DMFE_DBUG(0, "dm9000_hash_table()", 0); /* Set Node address */ for (i = 0, oft = 0x10; i < 6; i++, oft++) iow(db, oft, dev->dev_addr[i]); /* Clear Hash Table */ for (i = 0; i < 4; i++) hash_table[i] = 0x0; /* broadcast address */ hash_table[3] = 0x8000; /* the multicast address in Hash Table : 64 bits */ for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { hash_val = cal_CRC((char *)mcptr->dmi_addr, 6, 0) & 0x3f; hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); } /* Write the hash table to MAC MD table */ for (i = 0, oft = 0x16; i < 4; i++) { iow(db, oft++, hash_table[i] & 0xff); iow(db, oft++, (hash_table[i] >> 8) & 0xff); }}/* Calculate the CRC valude of the Rx packet flag = 1 : return the reverse CRC (for the received packet CRC) 0 : return the normal CRC (for Hash Table index)*/static unsigned long cal_CRC(unsigned char * Data, unsigned int Len, u8 flag){ u32 crc = ether_crc_le(Len, Data); if (flag) return ~crc; return crc; }/* Read a byte from I/O port*/static u8 ior(board_info_t *db, int reg){ outb(reg, db->io_addr); return inb(db->io_data);}/* Write a byte to I/O port*/static void iow(board_info_t *db, int reg, u8 value){ outb(reg, db->io_addr); outb(value, db->io_data);}/* Read a word from phyxcer*/static u16 phy_read(board_info_t *db, int reg){ /* Fill the phyxcer register into REG_0C */ iow(db, DM9KS_EPAR, DM9KS_PHY | reg); iow(db, DM9KS_EPCR, 0xc); /* Issue phyxcer read command */ udelay(100); /* Wait read complete */ iow(db, DM9KS_EPCR, 0x0); /* Clear phyxcer read command */ /* The read data keeps on REG_0D & REG_0E */ return ( ior(db, DM9KS_EPDRH) << 8 ) | ior(db, DM9KS_EPDRL); }/* Write a word to phyxcer*/static void phy_write(board_info_t *db, int reg, u16 value){ /* Fill the phyxcer register into REG_0C */ iow(db, DM9KS_EPAR, DM9KS_PHY | reg); /* Fill the written data into REG_0D & REG_0E */ iow(db, DM9KS_EPDRL, (value & 0xff)); iow(db, DM9KS_EPDRH, ( (value >> 8) & 0xff)); iow(db, DM9KS_EPCR, 0xa); /* Issue phyxcer write command */ udelay(500); /* Wait write complete */ iow(db, DM9KS_EPCR, 0x0); /* Clear phyxcer write command */}#ifdef MODULEMODULE_LICENSE("GPL");MODULE_DESCRIPTION("Davicom DM9000A/DM9010 ISA/uP Fast Ethernet Driver");MODULE_PARM(mode, "i");MODULE_PARM(irq, "i");MODULE_PARM(iobase, "i");MODULE_PARM_DESC(mode,"Media Speed, 0:10MHD, 1:10MFD, 4:100MHD, 5:100MFD");MODULE_PARM_DESC(irq,"EtherLink IRQ number");MODULE_PARM_DESC(iobase, "EtherLink I/O base address");/* Description: when user used insmod to add module, system invoked init_module() to initilize and register.*/int init_module(void){ switch(mode) { case DM9KS_10MHD: case DM9KS_100MHD: case DM9KS_10MFD: case DM9KS_100MFD: media_mode = mode; break; default: media_mode = DM9KS_AUTO; } dmfe_dev = dmfe_probe1(); if(IS_ERR(dmfe_dev)) return PTR_ERR(dmfe_dev); return 0;}/* Description: when user used rmmod to delete module, system invoked clean_module() to un-register DEVICE.*/void cleanup_module(void){ struct net_device *dev = dmfe_dev; DMFE_DBUG(0, "clean_module()", 0); unregister_netdev(dmfe_dev); release_region(dev->base_addr, 2);#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) kfree(dev);#else free_netdev(dev);#endif DMFE_DBUG(0, "clean_module() exit", 0);}#endif
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