mvd.h

一个两碟控制的VCD的代码,两碟之间的转动及连续播放,已大量生产的CODE.

/* Copyright 1996, ESS Technology, Inc.					*/
/* SCCSID @(#)mvd.h	1.6 2/3/98 */

/*
 * $Log$
 */

#ifndef FAKE
#ifndef _MVD_H_
#define _MVD_H_

/*
 * EXAMPLE:
 * --------
 * #include "mvd.h"
 *
 * register volatile int *mvd asm("r27");
 *
 * main()
 * {
 *     int read_value;
 *     mvd = (int *)OMNI_BASE;
 *     mvd[ riface_reflect ] = 0x3b;
 *     read_value = mvd[ riface_reflect ];    (read_value should be 0xdc) 
 * }
 *
 */
#define OMNI_BASE    0x20000000    /* ALL VCP registers are off this */

/* The following Defines were machine generated from MVD.ERS */
/* the program checks for address uniqueness, and WORD boundary */

#define vid_scn_hstart                  0x0400          /* 20001000 */
#define vid_scn_hend                    0x0401          /* 20001004 */
#define vid_scn_vstart                  0x0402          /* 20001008 */
#define vid_scn_vend                    0x0403          /* 2000100c */
#define vid_scn_vertirq                 0x0404          /* 20001010 */
#define vid_scn_hblank_start            0x0405          /* 20001014 */
#define vid_scn_hblank_stop             0x0406          /* 20001018 */
#define vid_scn_vblank_start            0x0407          /* 2000101c */
#define vid_scn_vblank_stop             0x0408          /* 20001020 */
#define vid_scn_hsyncwidth              0x0409          /* 20001024 */
#define vid_scn_hsyncperiod             0x040a          /* 20001028 */
#define vid_scn_vsyncperiod             0x040b          /* 2000102c */
#define vid_scn_vsyncpixel              0x040c          /* 20001030 */
#define vid_scn_vsyncwidth              0x040e          /* 20001038 */
#define vid_scn_counter_ctl             0x040f          /* 2000103c */
#define vid_scn_horizcount              0x0410          /* 20001040 */
#define vid_scn_vertcount               0x0411          /* 20001044 */
#define vid_scn_outputcntl              0x0440          /* 20001100 */
#define vid_scn_outputstatus            0x0441          /* 20001104 */
#define vid_scn_resets                  0x0480          /* 20001200 */
#define vid_scn_uv_wordsize             0x0481          /* 20001204 */
#define vid_scn_vertsize                0x0482          /* 20001208 */
#define vid_scn_incval                  0x0483          /* 2000120c */
#define vid_scn_uv_startstop            0x0484          /* 20001210 */
#define vid_scn_y_wordsize              0x0485          /* 20001214 */
#define vid_scn_y_startstop             0x0486          /* 20001218 */
#define vid_scn_misc0                   0x0487          /* 2000121c */
#define vid_scn_status                  0x0488          /* 20001220 */
#define vid_scn_misc1                   0x0489          /* 20001224 */
#define vid_scn_nrfiltertable           0x04c0          /* 20001300 */
#define vid_scn_y_coefficients          0x0500          /* 20001400 */
#define vid_scn_uv_coefficients         0x0540          /* 20001500 */
#define vid_scn_osd_hstart              0x0444          /* 20001110 */
#define vid_scn_osd_hend                0x0445          /* 20001114 */
#define vid_scn_osd_vstart              0x0446          /* 20001118 */
#define vid_scn_osd_vend                0x0447          /* 2000111c */
#define vid_scn_osd_startstop           0x0448          /* 20001120 */
#define vid_scn_osd_misc                0x0449          /* 20001124 */
#define vid_scn_osd_clrint              0x044a          /* 20001128 */
#define vid_scn_osd_palette             0x0450          /* 20001140 */

#define r_hostdmaport                   0x0c00          /* 20003000 */
#define r_hostvcxport                   0x0c01          /* 20003004 */
#define r_hostdbgport                   0x0c02          /* 20003008 */
#define r_hostctl                       0x0c03          /* 2000300c */
#define r_hostmask                      0x0c04          /* 20003010 */
#define r_hostirqstat                   0x0c05          /* 20003014 */

#define xpll_direct                     0x0d03          /* 2000340c */
#define xpll_freq                       0x0d01          /* 20003404 */
#define xpll_slew                       0x0d02          /* 20003408 */
#define xpll_cont                       0x0d00          /* 20003400 */

#define xport_microcode_table           0x0e00          /* 20003800 */
#define xport_pid_table                 0x0e80          /* 20003a00 */
#define xport_crc_data			0x0ea0		/* 20003a80 */
#define xport_pc                        0x0ee0          /* 20003b80 */
#define xport_misc                      0x0ee1          /* 20003b84 */
#define xport_interupt_mask             0x0ee2          /* 20003b88 */
#define xport_input_mode                0x0ee3          /* 20003b8c */
#define xport_flush_output              0x0ee4          /* 20003b90 */
#define xport_clear_stat_bits           0x0ee5          /* 20003b94 */
#define xport_read_risc_data            0x0ee0          /* 20003b80 */
#define xport_read_status               0x0ee1          /* 20003b84 */
#define xport_read_rff_count            0x0ee2          /* 20003b88 */
#define xport_read_cam_channel          0x0ee3          /* 20003b8c */
#define xport_read_irq_stat		0x0ee4          /* 20003b90 */
#define xport_read_ostate               0x0ee5          /* 20003b94 */
#define xport_read_ndata                0x0ee6          /* 20003b98 */   
#define xport_read_ndat2                0x0ee7          /* 20003b9c */

#define riface_width         		0x1000		/* 20004000 */
#define riface_wait_state    		0x1001		/* 20004004 */
#define riface_turnoff_delay 		0x1002		/* 20004008 */
#define riface_timer1        		0x1003		/* 2000400c */
#define riface_clear_timer1  		0x1004		/* 20004010 */
#define riface_timer2        		0x1005		/* 20004014 */
#define riface_clear_timer2  		0x1006		/* 20004018 */
#define riface_power_save    		0x1007		/* 2000401c */
#define riface_reflect       		0x1008		/* 20004020 */
#define riface_clear_dbgirq		0x1009		/* 20004024 */
#define riface_irqsuppress   		0x100a		/* 20004028 */
#define riface_aux1          		0x100b		/* 2000402c */
#define riface_aux2          		0x100c		/* 20004030 */
#define riface_irqmask       		0x100d		/* 20004034 */
#define riface_irqstatus     		0x100e		/* 20004038 */

#define rdma_transr_addr                0x1800          /* 20006000 */
#define rdma_tdmw_addr              	0x1804          /* 20006010 */
#define rdma_gatewayr_addr              0x1808          /* 20006020 */
#define rdma_gatewayw_addr              0x180c          /* 20006030 */
#define rdma_hostr_addr                 0x1810          /* 20006040 */
#define rdma_hostw_addr                 0x1814          /* 20006050 */
#define rdma_tdmr_addr              	0x1818          /* 20006060 */
#define rdma_transr_cnt                 0x1801          /* 20006004 */
#define rdma_tdmw_cnt               	0x1805          /* 20006014 */
#define rdma_gatewayr_cnt               0x1809          /* 20006024 */
#define rdma_gatewayw_cnt               0x180d          /* 20006034 */
#define rdma_hostr_cnt                  0x1811          /* 20006044 */
#define rdma_hostw_cnt                  0x1815          /* 20006054 */
#define rdma_tdmr_cnt               	0x1819          /* 20006064 */
#define rdma_transr_pri                 0x1802          /* 20006008 */
#define rdma_tdmw_pri               	0x1806          /* 20006018 */
#define rdma_gatewayr_pri               0x180a          /* 20006028 */
#define rdma_gatewayw_pri               0x180e          /* 20006038 */
#define rdma_hostr_pri                  0x1812          /* 20006048 */
#define rdma_hostw_pri                  0x1816          /* 20006058 */
#define rdma_tdmr_pri               	0x181a          /* 20006068 */
#define rdma_enable                     0x1840          /* 20006100 */
#define rdma_done                       0x1841          /* 20006104 */
#define rdma_pageaddress                0x1842          /* 20006108 */
#define rdma_donemask                   0x1843          /* 2000610c */
#define rdma_disable                    0x1844          /* 20006110 */
#define rdma_status                     0x1847          /* 2000611c */
#define rdma_reset                      0x1845          /* 20006114 */

#define buscon_vp_control               0x2000          /* 20008000 */
#define buscon_vp_stat                  0x2001          /* 20008004 */
#define buscon_dram_control             0x2040          /* 20008100 */
#define buscon_dram_reftime             0x2041          /* 20008104 */
#define buscon_dma_floating             0x2042          /* 20008108 */
#define buscon_dma_rdreflev             0x2043          /* 2000810c */
#define buscon_cmdque_vpdeltas          0x2080          /* 20008200 */
#define buscon_cmdque_vpstatwait        0x2081          /* 20008204 */
#define buscon_cmdque_vpdmax            0x2082          /* 20008208 */
#define buscon_cmdque_vpdmay            0x2083          /* 2000820c */
#define buscon_cmdque_vprd              0x2084          /* 20008210 */
#define buscon_cmdque_vpcbuswr          0x2085          /* 20008214 */
#define buscon_cmdque_vpdbuswrlow       0x2086          /* 20008218 */
#define buscon_cmdque_vpdbuswrhi        0x2087          /* 2000821c */
#define buscon_cmdque_cntl              0x2088          /* 20008220 */
#define buscon_cmdque_status            0x2089          /* 20008224 */
#define buscon_cmdque_test              0x208a          /* 20008228 */
#define buscon_cmdque_numentries        0x208b          /* 2000822c */
#define test_buscon_dma_deltas_vp       0x2100          /* 20008400 */
#define buscon_dma_deltas_ysn           0x2101          /* 20008404 */
#define buscon_dma_deltas_ysc           0x2102          /* 20008408 */
#define buscon_dma_deltas_usc           0x2103          /* 2000840c */
#define buscon_dma_deltas_vsc           0x2104          /* 20008410 */