monboot.s

一个两碟控制的VCD的代码,两碟之间的转动及连续播放,已大量生产的CODE.

; Copyright 1998, ESS Technology, Inc
; SCCSID @(#)monboot.s	1.1 1/15/98
; 
;	$Log$
;
; This version is based on version 1.21 of startup.s
;
; ROM loader source code.
;
; Assemble and link with the following switches:
;       ax -R startup.s
;       ld  -Ttext 0cfffde4 -e powerup -X -o startup.sun startup.o
; Notice that we want the code to start at 0cfffe04, since there is a
; 20h-byte header, we set the starting point of text to 0cfffde4.
;
; IMPORTANT : See ERS to see how to set RIFACE_WIDTH and RIFACE_WAITSTATE
;             for different bank used as EPROM
;
; This file uses Bank3 as example
;
; address 4xxxxxx for bank1
; address 8xxxxxx for bank2
; address Cxxxxxx for bank3
;
; WHEN MAKING CHANGES TO THIS CODE, MAKE SURE THE FOLLOWING TWO LOCATIONS 
; REMAIN UNCHANGED:
;       powerup :     0x 0cff ff80
;       LastLoc :     0x 0cff fffc
;
; This code accomplishes the following three things:
;       1) Set up PSW
;       2) Read commands and arguments prestored in ROM, and execute the
;          commands to download code from ROM to SRAM.
;       3) As the last step, a jump command is expected to goto a location
;          specified by the argument. After a jump command, this code will
;          never get control again.
;
; Diagram of ROM (suppose EPROM bank3 address base is 0xc000000)
;   ROM base |--------------|
;  0xc000000 | ROM header   | size = 16 Bytes
;            |--------------|
;            | file 1       |
;            |--------------|
;                  .
;           file 2 -- file N-1  
;                  .
;            |--------------|
;            | file N       |
;            |--------------|
;            | command      | size = 4 * 4 * cmdblkn (Bytes)
;            | block        |
;            |--------------| 
;            |              |
;            |--------------| 
;            | boot code    | entry point always set at 0x0cffff80
;            |--------------| 
; 0x0cfffffc | address of   | 4 Bytes
;            | ROM header   |
;            |--------------| 
;
; Since ESS' ROM emulator uses locations 0xc000000 and 0xc000004 to
; communicate with the PC host, newer code usually starts at 0xc040000.
; Since ROM is only 128K/256K, 0xc040000 is effectly the same as 0xc000000 
; from ROM's point's of view; however, emulator can depend on the bit 18
; to differentiate ROM access versus emulator access.
;
; ROM header:
;	1) Version (usually is the date when the ROM is made) (4B)
;	2) Starting location of command block (4B)
;	3) Number of entris in command block (4B)
;	4) Number of files (4B)
;		
; ROM loader supports the folowing commands:
;       1) COPY(1) : download data from ROM to SRAM
;               Arguments : ROM_addr SRAM_addr size
;		where:
;                 - ROM_addr  is the byte address of data to be downloaded
;                 - SRAM_addr is the target byte address to write to
;                 - size      is the dword size of data to be written
;       2) CLEAR(2) : clear a piece of SRAM to 0
;               Arguments : SRAM_addr size
;		where:
;                 - SRAM_addr is the starting byte address to be cleared
;                 - size      is the dword size of SRAM to be cleared
;       3) JUMP(3) : jump to the given address
;               Arguments : address
;		where:
;                 - address is the dword address of target code
;       4) JSR(4) : call subroutine at given address
;               Arguments : address
;		where:
;                 - address is the dword address of target subroutine
;       5) SET24(5) : set value of r24
;               Arguments: value
;		where:
;                 - value is the value
;       6) SET25(6) : set value of r25
;               Arguments: value
;		where:	
;                 - value is the value
;       7) SET23(7) : set value of r23
;               Arguments: value
;		where:	
;                 - value is the value	
; Address of romheader is given at address 0x0cfffffc (LastLoc),
; This is done by rom2
;
; The following macros have to be modified for various different setup:
; 	0x7
;		0x7	for bank 0 (simulation)
;		0x4ff	for bank 1
;		0x8ff	for bank 2
;		0xcff	for bank 3
;
; 	0x7ff
;		see ERS
;
; 	0x801d 
;		see ERS
;

        .data
        .globl dstart
dstart:
        .globl _environ
_environ:

        .text
	.globl powerup
        .globl tstart
        .globl _tstart
        .globl LastLoc
	.noreorg
	
        .def    RIFACE_WIDTH            =0x20004000
        .def    RIFACE_WAIT_STATE       =0x20004004
        .def    RIFACE_TURNOFF_DELAY    =0x20004008

tstart:
_tstart:

ParseCmd:
; struct romheader {
;    longword version;
;    longword cmdblkptr;        /* location of commands and arguments   */
;    longword cmdblkn;          /* number of commands to be executed    */
;    longword nfiles;           /* number of files in ROM               */
; } header;
; Each command occupies 4 dwords, the first one is command type, the other
; three are arguments
; Temp variables:
;       r9 : address of romheader
;       r10: start address of command block
;       r11: number of commands to be executed
;
	addi r0,#0,r26			 ; Clear r26
        addi r0,#0x1cff,r9         	 ; r9 = first half of last ROM loc.
        sh   r0,r9,r9,#16                ; r9 << = 16 (0xcff0000)
        addi r9,#0xfffc,r9               ; r9 = 0xcfffffc
        ld   0x0[r9],r9                  ; r9 : location of romheader
        nop
        st   0xc[r0],r9                  ; save it
        nop
        ld   0x14[r9],r10                 ; r10 = cmdblkptr
        nop
        st   0x10[r0],r10                ; save it
        nop
        ld   0x18[r9],r11                 ; r11 = cmdblkn
        nop
        st   0x14[r0],r11
        nop
        mov  r0,r7                       ; r7 : loop counter for
                                         ; executed commands 

LoopCmd:
        ld   0x0[r10],r3                 ; r3 : first 4B is cmd type
        addi r0,#0x1,r2                  ; r2 = 1 (COPY)
        beq  r2,r3,Copy                  ; goto Copy
        addi r0,#0x2,r2                  ; r2 = 2 (CLEAR)
        nop
        beq  r2,r3,Clear                 ; goto Clear
        addi r0,#0x3,r2                  ; r2 = 3 (JUMP)
        nop
        beq  r2,r3,Jump                  ; goto Jump
        addi r0,#0x4,r2                  ; r2 = 4 (JSR)
        nop
        beq  r2,r3,Jsr                   ; goto Jsr
        addi r0,#0x5,r2                  ; r2 = 5 (SET24)
        nop
        beq  r2,r3,Set24                 ; goto Set24
        addi r0,#0x6,r2                  ; r2 = 6 (SET25)
        nop
        beq  r2,r3,Set25                 ; goto Set25
        addi r0,#0x7,r2                  ; r2 = 7 (SET23)
        nop
        beq  r2,r3,Set23                 ; goto Set23
        nop
        nop


NextCmd:
        addi r7,#0x1,r7                  ; increment loop counter
        addi r10,#0x10,r10               ; move pointer to next cmdblk
        bne  r7,r11,LoopCmd              ; loop if not done
        nop
        nop

Copy:
; copy data from source address to destination address
; arguments : src_addr, dest_addr, size
; Temp variables:
;       r4 : address of source data
;       r5 : address of destination
;       r6 : loop counter
;       r10: start address of command arguments
;
        ld   0x4[r10],r4                 ; address of source data
        ld   0x8[r10],r5                 ; address of destination
        ld   0xc[r10],r6                 ; r6 : loop countersize to copy
        nop
        beq   r0,r6,NextCmd              ; do copy if size > 0
        nop
        nop

LoopCopy:                                    
        ld   0x0[r4],r2                  ; load one dword
        nop
        nop                                  
        st   0x0[r5],r2                  ; copy to dest
        nop
        addi r4,#0x4,r4                  ; move pointer to next dword data
        addi r5,#0x4,r5                  ; move pointer to next target address
        addi r6,#-1,r6                   ; decrement loop counter
        bne  r6,r0,LoopCopy              ; loop copy
        nop
        nop
        beq   r0,r0,NextCmd              ; continue to next command if done
        nop
        nop
        
Clear:
; clear memory starting from given address to 0
; arguments : start_addr, size
; Temp variables:
;       r4 : address of source data
;       r6 : loop counter
;       r10: start address of command arguments
;
        ld   0x4[r10],r4                 ; starting address to clear
        ld   0x8[r10],r6                 ; loop counter : size to clear
        nop
        beq   r0,r6,NextCmd              ; do clear if size >0
        nop
        nop

LoopClear:
        st   0x0[r4],r0                  ; clear one dword
        nop
        addi r4,#0x4,r4                  ; move to next address
        addi r6,#-1,r6                   ; decrement loop counter
        bne  r6,r0,LoopClear             ; loop clear
        nop
        nop
        beq   r0,r0,NextCmd              ; continue to next command if done
        nop
        nop

Set25:
; set new value of r25
; arguments : value
; Temp variables:
;       r10: start address of command arguments
;
        beq  r0,r0,NextCmd               ; continue to next command
        ld   0x4[r10],r25                ; r25 = value
        nop


Set24:
; set new value of r24
; arguments : value
; Temp variables:
;       r10: start address of command arguments
;
        beq  r0,r0,NextCmd               ; continue to next command
        ld   0x4[r10],r24                ; r24 = value
        nop

Set23:
; set new value of r23
; arguments : value
; Temp variables:
;       r10: start address of command arguments
;
        beq  r0,r0,NextCmd               ; continue to next command
        ld   0x4[r10],r23                ; r23 = value
        nop

        
Jump:
; jump to given address
; arguments : dest_addr
; Temp variables:
;       r4 : address to jump to
;       r10: start address of command arguments
;
        ld   0x4[r10],r4                 ; r4 : address to jump
        nop
        jspci   r4,#0x0,r0               ; jump
	nop
	nop

Jsr:
; call subroutine starting at given address
; arguments : subroutine_addr
; Temp variables:
;       r4 : address to jump to
;       r10: start address of command arguments
;
        ld   0x4[r10],r4                 ; address to jump 
        nop
        st   0x20[r0],r6
        st   0x24[r0],r7
        jspci    r4,#0x0,r31
        st   0x28[r0],r10
        st   0x2c[r0],r11                ; save registers
        ld   0x20[r0],r6
        ld   0x24[r0],r7
        beq   r0,r0,NextCmd              ; continue to next command 
        ld   0x28[r0],r10
        ld   0x2c[r0],r11                ; restore registers

; Power up always starts here
; Temp. vars:
;	r1:	PSW
;	r2:	MEMWIDTH/mask
;	r3:	MEMDELAY
;	r5:	12000000h
;	r6;	10000000h
;	r21:	Read back from 10000000 (c3h is 3210!!)
;       r27:    omnibase
powerup:
        addi r0,#0xc3,r1
        movtos r1,psw			 ; set PSW
        addi r0,#0x2000,r27              ; r27 = 0x2000
        sh   r0,r27,r27,#16              ; r27 = r27 << 16 (i.e. omnibase)

	addi r0,#0x1200,r5
	sh   r0,r5,r5,#16		 ; r5 -> non-cachable DRAM 0
	addi r0,#0x1000,r6
	sh   r0,r6,r6,#16		 ; r6 -> non-cachable 0
					 ; (SRAM for 3208, DRAM for 3210)
	addi r0,#_WIDTH10_,r2	 	 ; Width for 3210 (bank 0 is DRAM)
	st   0x4000[r27],r2		 ; Set RIFACE_WIDTH

	; If the chip is 3210, then we can write to DRAM location and
	; read it back from the same location from bank 0. If the chip
	; is 3208, then bank 0 is not DRAM due to RIFACE_WIDTH set up
	st   0x1000[r5],r1		 ; Write 0xc3 to 0x12001000
	st   0x0000[r5],r0		 ; Change the data bus value in case
					 ; capacitor holds r1 value for the
					 ; next read
	ld   0x1000[r6],r21		 ; Read from 0x10000000
	addi r0,#0xff,r2		 ; r2 = 0xff (mask)
	and  r21,r2,r21			 ; Only look at the last 8b
	beq  r1,r21,set_delay
        addi r0,#_MEMDELAYH_,r3          ; r3  = 0x1d (3208 + wait state)
					 ; (Load delay)
        sh   r0,r3,r3,#16                ; r3  << = 16 (0x1d0000)

es3208:
	addi r0,#_MEMWIDTH_,r2		 ; r2 holds width setting for 3208
	st   0x4000[r27],r2		 ; Set RIFACE_WIDTH for 3208

set_delay:
        addi r3,#_MEMDELAYL_,r3          ; r3  = Wait states of memory banks
					 ; 1d001e = 1 (0x1a, 0, 0, 0x1e) or
					 ; 1d801e = 1 (0x1b, 0, 0, 0x1e)
					 ; which means: 3208
					 ; bank3:  5 (1a) or 4 (1b) wait states
					 ; bank2: 32 wait states
					 ; bank1: 32 wait states
					 ; bank0:  1 wait states
        st   0x4004[r27],r3              ; set RIFACE_WAIT_STATE
					 ; Bank3 : 3 wait state
        addi r0,#0x204,r2                ; r2  = DRAM configuration (.5MB)
					 ; Browser board can also be set to
					 ; 0x2ea
        st   0x8100[r27],r2              ; set buscon_dram_control
        st    0x0[r5],r21		 ; If it is 0xc3, then it is 3210;
					 ; Otherwise, it is 3208
        nop
        nop
        nop

        beq   r0,r0,ParseCmd             ; goto ParseCmd
	nop
        nop
LastLoc:
        nop