📄 dsc.h
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/* Copyright 1997, ESS Technology, Inc. */
/* SCCSID @(#)dsc.h 1.40 6/9/98 */
/*
* $Log$
*/
#ifndef _DSC_H_
#define _DSC_H_
#ifdef DSC
#ifndef _COMMON_H_
#include "common.h"
#endif
#ifndef __IOPORT_H__
#include "ioport.h"
#endif
#define dsc_aux_mode 0x00 /* 3217 family */
#define dsc_aux_modem 0x01
#define dsc_cchip_ctl 0x02
#define dsc_cchip_ctlm 0x03
#define dsc_clkctl 0x04
#define dsc_clkctlm 0x05
#define dsc_watchdog 0x06
#define dsc_watchdogm 0x07
#define dsc_aux0_data 0x08
#define dsc_aux0_datam 0x09
#define dsc_aux0_ctl 0x0a
#define dsc_aux0_ctlm 0x0b
#define dsc_aux1_data 0x0c
#define dsc_aux1_datam 0x0d
#define dsc_aux1_ctl 0x0e
#define dsc_aux1_ctlm 0x0f
#define dsc_subq_ctl 0x20 /* 3217 family */
#define dsc_subq_ctlm 0x21
#define dsc_subq_bcnt 0x22 /* 3217 family */
#define dsc_subq_bcntm 0x23
#define dsc_subq_data 0x24 /* 3217 family */
#define dsc_subq_datam 0x25
#define dsc_vfd_ctl 0x26 /* 3217 family */
#define dsc_vfd_ctlm 0x27
#define dsc_vfd_data 0x28 /* 3217 family */
#define dsc_vfd_datam 0x29
#define dsc_irq_ctl 0x2a /* 3217 family */
#define dsc_irq_ctlm 0x2b
#define dsc_sys_status 0x2c /* 3217 family */
#define dsc_sys_statusm 0x2d
#define dsc_ir_diff 0x2e /* 3217 family */m
#define dsc_ir_diffm 0x2f
#define dsc_dvectl1 0x40
#define dsc_dvectl1m 0x41
#define dsc_dvectl2 0x42
#define dsc_dvectl2m 0x43
#define dsc_dvectl3 0x44
#define dsc_dvectl3m 0x45
#define dsc_dvectl4 0x46
#define dsc_dvectl4m 0x47
#define dsc_dvectl5 0x48
#define dsc_dvectl5m 0x49
#define dsc_dvetdat1 0x4a
#define dsc_dvetdat1m 0x4b
#define dsc_dvetdat2 0x4c
#define dsc_dvetdat2m 0x4d
#define dsc_dvetdat3 0x4e
#define dsc_dvetdat3m 0x4f
#define dsc_dvecc1 0x60 /* 3217 family */
#define dsc_dvecc1m 0x61
#define dsc_dvecc2 0x62 /* 3217 family */
#define dsc_dvecc2m 0x63
#define dsc_dvecc3 0x64 /* 3217 family */
#define dsc_dvecc3m 0x65
#define dsc_dvecc4 0x66 /* 3217 family */
#define dsc_dvecc4m 0x67
#define dsc_dvecc5 0x68 /* 3217 family */
#define dsc_dvecc5m 0x69
#define dsc_dvemv1 0x6a /* 3217 family */
#define dsc_dvemv1m 0x6b
#define dsc_dvemv2 0x6c /* 3217 family */
#define dsc_dvemv2m 0x6d
#define dsc_audioxmt1 0x80
#define dsc_audioxmt1m 0x81
#define dsc_audioacnt0l 0x84
#define dsc_audioacnt0lm 0x85
#define dsc_audioacnt0h 0x86
#define dsc_audioacnt0hm 0x87
#define dsc_audioacnt1l 0x88
#define dsc_audioacnt1lm 0x89
#define dsc_audioacnt1h 0x8a
#define dsc_audioacnt1hm 0x8b
#define dsc_audioapllm 0x8c
#define dsc_audioapllmm 0x8d
#define dsc_audioaplln 0x8e
#define dsc_audioapllnm 0x8f
#define dsc_audiorcv1 0xc0
#define dsc_audiorcv1m 0xc1
#define dsc_audiorcv2 0xc2
#define dsc_audiorcv2m 0xc3
#define dsc_audioadc1 0xc4
#define dsc_audioadc1m 0xc5
#define dsc_audioadc2 0xc6
#define dsc_audioadc2m 0xc7
#define dsc_audiodbg 0xc8
#define dsc_audiodbgm 0xc9
#define dsc_audiovocal 0xca /* 3217 family */
#define dsc_audiovocalm 0xcb
extern unsigned int DSC_cmd(unsigned int, unsigned int);
extern void DSC_encoder_off(void);
extern void DSC_getstatus(void);
extern void DSC_init(void);
extern void DSC_init_ir(int, int, int);
extern void DSC_init_s0s1(int, int, int);
extern void DSC_init_16550(int, int);
extern void DSC_init_c2po(int, int);
extern void DSC_mute_on(void);
extern void DSC_powerdown(void);
extern void DSC_powerup(void);
extern void DSC_reset_audio(void);
extern void DSC_s_video(int);
extern void DSC_set_aux(int, int, int);
extern void DSC_set_TV(int);
extern void DSC_toggle(void);
#if (CUST71 && C80)
extern void DSC_mute_off(void);
#endif
#ifdef ECHO
extern void DSC_mic_on(void);
extern void DSC_mic_off(void);
#endif
/* Macros to set AUX pins on 3205/7/9 side */
#define SET_EAUX0 DSC_set_aux(0, 1, 0x1)
#define SET_EAUX1 DSC_set_aux(0, 1, 0x2)
#define SET_EAUX2 DSC_set_aux(0, 1, 0x4)
#define SET_EAUX3 DSC_set_aux(0, 1, 0x8)
#define SET_EAUX4 DSC_set_aux(0, 1, 0x10)
#define SET_EAUX5 DSC_set_aux(0, 1, 0x20)
#define SET_EAUX6 DSC_set_aux(0, 1, 0x40)
#define SET_EAUX7 DSC_set_aux(0, 1, 0x80)
#define SET_EAUX8 DSC_set_aux(1, 1, 0x1)
#define SET_EAUX9 DSC_set_aux(1, 1, 0x2)
#define SET_EAUX10 DSC_set_aux(1, 1, 0x4)
#define SET_EAUX11 DSC_set_aux(1, 1, 0x8)
#define SET_EAUX12 DSC_set_aux(1, 1, 0x10)
#define SET_EAUX13 DSC_set_aux(1, 1, 0x20)
#define SET_EAUX14 DSC_set_aux(1, 1, 0x40)
#define SET_EAUX15 DSC_set_aux(1, 1, 0x80)
#define SET_ALL_EAUX DSC_set_aux(0, 1, 0xff); DSC_set_aux(1, 1, 0xff)
/* Macros to clear AUX pins on 3205/7/9 side */
#define CLEAR_EAUX0 DSC_set_aux(0, 0, 0x1)
#define CLEAR_EAUX1 DSC_set_aux(0, 0, 0x2)
#define CLEAR_EAUX2 DSC_set_aux(0, 0, 0x4)
#define CLEAR_EAUX3 DSC_set_aux(0, 0, 0x8)
#define CLEAR_EAUX4 DSC_set_aux(0, 0, 0x10)
#define CLEAR_EAUX5 DSC_set_aux(0, 0, 0x20)
#define CLEAR_EAUX6 DSC_set_aux(0, 0, 0x40)
#define CLEAR_EAUX7 DSC_set_aux(0, 0, 0x80)
#define CLEAR_EAUX8 DSC_set_aux(1, 0, 0x1)
#define CLEAR_EAUX9 DSC_set_aux(1, 0, 0x2)
#define CLEAR_EAUX10 DSC_set_aux(1, 0, 0x4)
#define CLEAR_EAUX11 DSC_set_aux(1, 0, 0x8)
#define CLEAR_EAUX12 DSC_set_aux(1, 0, 0x10)
#define CLEAR_EAUX13 DSC_set_aux(1, 0, 0x20)
#define CLEAR_EAUX14 DSC_set_aux(1, 0, 0x40)
#define CLEAR_EAUX15 DSC_set_aux(1, 0, 0x80)
#define CLEAR_ALL_EAUX DSC_set_aux(0, 0, 0xff); DSC_set_aux(1, 0, 0xff)
/* Macros to tri-state AUX pins on 3205/7/9 side */
#define TRISTATE_EAUX0 DSC_set_aux(0, 2, 0x1)
#define TRISTATE_EAUX1 DSC_set_aux(0, 2, 0x2)
#define TRISTATE_EAUX2 DSC_set_aux(0, 2, 0x4)
#define TRISTATE_EAUX3 DSC_set_aux(0, 2, 0x8)
#define TRISTATE_EAUX4 DSC_set_aux(0, 2, 0x10)
#define TRISTATE_EAUX5 DSC_set_aux(0, 2, 0x20)
#define TRISTATE_EAUX6 DSC_set_aux(0, 2, 0x40)
#define TRISTATE_EAUX7 DSC_set_aux(0, 2, 0x80)
#define TRISTATE_EAUX8 DSC_set_aux(1, 2, 0x1)
#define TRISTATE_EAUX9 DSC_set_aux(1, 2, 0x2)
#define TRISTATE_EAUX10 DSC_set_aux(1, 2, 0x4)
#define TRISTATE_EAUX11 DSC_set_aux(1, 2, 0x8)
#define TRISTATE_EAUX12 DSC_set_aux(1, 2, 0x10)
#define TRISTATE_EAUX13 DSC_set_aux(1, 2, 0x20)
#define TRISTATE_EAUX14 DSC_set_aux(1, 2, 0x40)
#define TRISTATE_EAUX15 DSC_set_aux(1, 2, 0x80)
#define TRISTATE_ALL_EAUX DSC_set_aux(0, 2, 0xff); DSC_set_aux(1, 2, 0xff)
/* Macros to sense the AUX values on 3205/7/9 */
#define EAUX0_HIGH (DSC_cmd(dsc_aux0_datam, 0) & 0x1)
#define EAUX1_HIGH (DSC_cmd(dsc_aux0_datam, 0) & 0x2)
#define EAUX2_HIGH (DSC_cmd(dsc_aux0_datam, 0) & 0x4)
#define EAUX3_HIGH (DSC_cmd(dsc_aux0_datam, 0) & 0x8)
#define EAUX4_HIGH (DSC_cmd(dsc_aux0_datam, 0) & 0x10)
#define EAUX5_HIGH (DSC_cmd(dsc_aux0_datam, 0) & 0x20)
#define EAUX6_HIGH (DSC_cmd(dsc_aux0_datam, 0) & 0x40)
#define EAUX7_HIGH (DSC_cmd(dsc_aux0_datam, 0) & 0x80)
#define EAUX8_HIGH (DSC_cmd(dsc_aux1_datam, 0) & 0x1)
#define EAUX9_HIGH (DSC_cmd(dsc_aux1_datam, 0) & 0x2)
#define EAUX10_HIGH (DSC_cmd(dsc_aux1_datam, 0) & 0x4)
#define EAUX11_HIGH (DSC_cmd(dsc_aux1_datam, 0) & 0x8)
#define EAUX12_HIGH (DSC_cmd(dsc_aux1_datam, 0) & 0x10)
#define EAUX13_HIGH (DSC_cmd(dsc_aux1_datam, 0) & 0x20)
#define EAUX14_HIGH (DSC_cmd(dsc_aux1_datam, 0) & 0x40)
#define EAUX15_HIGH (DSC_cmd(dsc_aux1_datam, 0) & 0x80)
#define EAUX0_LOW (!EAUX0_HIGH)
#define EAUX1_LOW (!EAUX1_HIGH)
#define EAUX2_LOW (!EAUX2_HIGH)
#define EAUX3_LOW (!EAUX3_HIGH)
#define EAUX4_LOW (!EAUX4_HIGH)
#define EAUX5_LOW (!EAUX5_HIGH)
#define EAUX6_LOW (!EAUX6_HIGH)
#define EAUX7_LOW (!EAUX7_HIGH)
#define EAUX8_LOW (!EAUX8_HIGH)
#define EAUX9_LOW (!EAUX9_HIGH)
#define EAUX10_LOW (!EAUX10_HIGH)
#define EAUX11_LOW (!EAUX11_HIGH)
#define EAUX12_LOW (!EAUX12_HIGH)
#define EAUX13_LOW (!EAUX13_HIGH)
#define EAUX14_LOW (!EAUX14_HIGH)
#define EAUX15_LOW (!EAUX15_HIGH)
#define GET_EAUX7_0 (DSC_cmd(dsc_aux0_datam, 0) & 0xff)
#define GET_EAUX15_8 (DSC_cmd(dsc_aux1_datam, 0) & 0xff)
/* For 3881/3883 */
/* May need the following macros to initialize EAUX values */
#define SET_SQCK SET_EAUX10
#define CLEAR_IRQOUT CLEAR_EAUX11
#define TRISTATE_SQSO TRISTATE_EAUX9
#define TRISTATE_C2PO TRISTATE_EAUX12
#define TRISTATE_16550 TRISTATE_EAUX13
#define TRISTATE_S0S1 TRISTATE_EAUX14
#define TRISTATE_IRIN TRISTATE_EAUX15
/* For dsc_irq_ctl */
#define DSC_RISING_EDGE 0 /* Trigger on rising edge */
#define DSC_FALLING_EDGE 1 /* Trigger on falling edge */
GBLDEF_0(int DSC_status, 0); /* Powerup cchip_ctl (warm boot?) */
#ifdef CLKDIV
/*
* New mechanism with newer revisions of 3210 (D and later):
* clkctl (PLL) is always set to 1 (i.e. 3210 depends on PLL for clock)
*
* Since we never use pass through mode for 3210's clock, we can use
* the clock divider to differentiate different power on/off states
* cchip_ctl clkctl (bit 0)
* (cold/warm) (divider) Cause Action
* =========================================================================
* cold (0) 0 A/C power on power down
* warm (1) 0 IR power off continue to standby
* warm (1) 1 IR power on or continue to power up
* watchdog reset
*
* Running: warm and 1 (11b)
* Standby: warm and 0 (10b)
* AC on: cold and don't care (00b)
*
* For RC5 (Philips-style remote control, bits 2,1 of clkctl (divider)
* indicates the last control bit (to prevent repeating of power up/down).
*/
#else
/* For older generatations of 3210 (revisions A, B, and C) */
/*
* cchip_ctl clkctl
* (cold/warm) (PLL) Cause Action
* =========================================================================
* cold (0) PLL (1) A/C power on power doen
* cold (0) bypass (0) IR power off continue to standby
* warm (1) PLL (1) IR power on or continue to power up
* watchdog reset
*
* Running: warm and PLL (11b)
* Standby: cold and bypass (00b)
* AC on: cold and PLL (01b)
*/
#endif
#define DSC_STATUS_STANDBY 0x0 /* Power down mode (standby) */
#define DSC_STATUS_ACON 0x1 /* First time A/C on */
#define DSC_STATUS_RUNNING 0x3 /* Power up mode (running) */
#define IS_POWER_DOWN (DSC_status == DSC_STATUS_STANDBY)
#ifdef DSC_IRQ
#define DSC_INIT_IR(on,edge,setmode) DSC_init_ir(on,edge,setmode)
#else
#define DSC_INIT_IR(on,edge,setmode)
#endif
#ifdef DSC_ENABLE_S0S1
#define DSC_INIT_S0S1(on,edge,count) DSC_init_s0s1(on,edge,count)
#else
#define DSC_INIT_S0S1(on,edge,count)
#endif
#ifdef DSC_ENABLE_16550
#define DSC_INIT_16550(on,edge) DSC_init_16550(on,edge)
#else
#define DSC_INIT_16550(on,edge)
#endif
#ifdef DSC_ENABLE_C2PO
#define DSC_INIT_C2PO(on,edge) DSC_init_c2po(on,edge)
#else
#define DSC_INIT_C2PO(on,edge)
#endif
#endif /* DSC */
/*
* Following routines are needed with or without 3207/9
*/
extern void DSC_dead(int); /* Reset the system */
#endif /* _DSC_H_ */
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