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📁 关于DVD的MPEG2用的DSP代码,在DSP的实现MPEG的压缩,解压算法.
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123 
#endif	// LS1888_TEST
	tst	r0,r2
	bne	Lupdate_fs

	// Error concealment below is needed for DVD (Evita T0-C5-00:19:15),
	// but not for VCD (C-Cube demo disc L-only/R-only)

        movb    r27,LBhdr_error_protection
        tsti    r27,0
        beq     Lupdate_fs
        mov     r27,Gb_Getbits_Ptr      // save Gb_Getbits_Ptr
        shl     r27,8                   // clear MS byte
        shr     r27,8                   // clear MS byte
        movh    r11,LIfrmsize
        addi    r11,0x10
        shl     r11,3                   // byte addr -> bit addr
seek_sync_next:
        jsr     r26,SUB_seek_sync_mpg
rtn_seek_sync_next:
        dlw     r0,SAMPLING_FREQ_TEMP   // Dumi: Getbit config need to be followed
        tsti    r10,F_SYNC_ERROR
        beq     error_handler_SS
        tsti    r11,0xc0
        bgte    seek_sync_next
        movi    Gb_Shadow_Ptr,0
        mupi    r0,0x8000
        or      r27,r0
        mov     Gb_Shadow_Ptr,r27
        nop
        nop
        gbi     r0,0x0
        dlw     r0,SAMPLING_FREQ_TEMP   // Dumi: Getbit config need to be followed
        j       Lupdate_fs
error_handler_SS:
        movi    Gb_Shadow_Ptr,0
        mupi    r0,0x8000
        or      r27,r0
        mov     Gb_Shadow_Ptr,r27
        nop
        nop
        gbi     r0,0x0
        dlw     r0,SAMPLING_FREQ_TEMP   // Dumi: Getbit config need to be followed
        j       error_handler

//-------- update sampling frequency --------
Lupdate_fs:
#if 	LS388

#if	EXTERNAL_A_CLOCK
#if QSOUND
	mupi	r4,MEM_SEG
	ori	r4,m48both
#endif	// QSOUND
	dlw	r2,VAL_PLL_CTRL_48K
	movb    r0,LBhdr_sampling_frequency
	tsti	r2,0
	beq	LoadHardCodedValue
	tsti	r0,1
	beq	Load48kPllValue
	dlw	r2,VAL_PLL_CTRL_44p1K
	dlw	r1,VAL_PLL_DIV_44p1K
	li	r3,CHANNEL_STATUS_441K
#if QSOUND
	mupi	r4,MEM_SEG
	ori	r4,m44both
#endif	// QSOUND
	j	checkPLLsetting

Load48kPllValue:
	dlw	r1,VAL_PLL_DIV_48K
	li	r3,CHANNEL_STATUS_48K
	j	checkPLLsetting

LoadHardCodedValue:
	rlwi	r1,Chip_Id
	tsti	r1,LS500_ID
	bne	Ls508PllValue
	li	r1,PLL_DIV_48K_500
	li	r2,PLL_CTRL_48K_500
	li	r3,CHANNEL_STATUS_48K
	tsti	r0,1
	beq	checkPLLsetting
	li	r1,PLL_DIV_441K_500
	li	r2,PLL_CTRL_441K_500
	li	r3,CHANNEL_STATUS_441K
#if QSOUND
	mupi	r4,MEM_SEG
	ori	r4,m44both
#endif	// QSOUND
	j	checkPLLsetting
Ls508PllValue:
	li	r1,PLL_DIV_48K_508
#if !LS1888_TEST
	li	r2,PLL_CTRL_48K_508
#else	// LS1888_TEST
	li	r2,PLL_CTRL_48K_1888
#endif	// LS1888_TEST
	li	r3,CHANNEL_STATUS_48K
	tsti	r0,1
	beq	checkPLLsetting
	li	r1,PLL_DIV_441K_508
#if !LS1888_TEST
	li	r2,PLL_CTRL_441K_508
#else	// LS1888_TEST
	li	r2,PLL_CTRL_441K_1888
#endif	// LS1888_TEST
	li	r3,CHANNEL_STATUS_441K
#if QSOUND
	mupi	r4,MEM_SEG
	ori	r4,m44both
#endif	// QSOUND
checkPLLsetting:
#if !LS1888_TEST
	rlwi	r0,PLL_Ctrl_Reg2
#else	// LS1888_TEST
	rlwi	r0,PLL_Ctrl_Reg1
#endif	// LS1888_TEST
	tst	r0,r2
	bne	Ladjust_pll
#if !LS1888_TEST
	rlwi	r0,PLL_Clk_Div_Reg
	tst	r0,r1
	beq	modify_sampling_freq_done
#endif	// LS1888_TEST

Ladjust_pll:
#if !LS1888_TEST
	rswi	r1,PLL_Clk_Div_Reg
#endif	// LS1888_TEST
	rswi	r3,SPDIF_channel_status
	nop
#if !LS1888_TEST
	rswi	r2,PLL_Ctrl_Reg2
#else	// LS1888_TEST
	rswi	r2,PLL_Ctrl_Reg1
#endif	// LS1888_TEST
	;;; update QExpander filter coefficient
	mupi	r3,MEM_SEG
	ori	r3,filterCoeffs
#if QSOUND
#if !THREE_STAGE
	loop	9,updateQExpander
#else	// !THREE_STAGE
	loop	7,updateQExpander
#endif	// !THREE_STAGE
	dlwr	r0,r4
	addi	r4,4
	dswr	r0,r3
	addi	r3,4
updateQExpander:
#endif	// QSOUND
	j	modify_sampling_freq_done
#endif	// EXTERNAL_A_CLOCK

#else	// LS388

        dlw     r0,SAMPLING_FREQ_TEMP
        movb    r1,LBhdr_sampling_frequency
        tst     r0,r1
        dsw     r1,SAMPLING_FREQ_TEMP
	beq	modify_sampling_freq_done

// set FIFO size

#if	SR48
	tsti	r1,SAMPLING_FREQ_480
	bne	Lfifo_sr48
	
	mupi    r0,MEM_SEG		//for 48kHz
        ori     r0,PCM_FIFO_0_START_44
        rswi    r0,PCM_FIFO_StartReg
        mupi    r0,MEM_SEG
        ori     r0,PCM_FIFO_1_END_44+4	//use smaller one at default
        rswi    r0,PCM_FIFO_EndReg
	j	Lcheck_spdif
	
Lfifo_sr48:				//for 44.1kHz
	mupi    r0,MEM_SEG
        ori     r0,PCM_FIFO_0_START
        rswi    r0,PCM_FIFO_StartReg
        mupi    r0,MEM_SEG
        ori     r0,PCM_FIFO_1_END+4	//use bigger for SR48
        rswi    r0,PCM_FIFO_EndReg

Lcheck_spdif:	
        dlw     r2,USER_ICFG
	movi    r0,Reg284PCM441
        andi    r2,ICFG_SPDIF_ENA
        tsti    r2,ICFG_SPDIF_ENA       // check SPDIF flag
        bne     Lnot_spdif

        mupi    r0,MEM_SEG
        ori     r0,PCM_FIFO_0_START_SP
        rswi    r0,PCM_FIFO_StartReg
        mupi    r0,MEM_SEG
        ori     r0,PCM_FIFO_1_END_SP+4
        rswi    r0,PCM_FIFO_EndReg

	movi    r0,Reg284PCM441_SP
        mupi    r2,0x0001
        ori     r2,0x0100
        or      r0,r2                   // enable SPDIF, disable LRCK
        mupi    r2,Reg298_PCM_up
        ori     r2,Reg298_441_dn
;        rswi    r2,SPDIF_channel_status
Lnot_spdif:	
#endif	//SR48
//---------
	
        dlw     r0,USER_ICFG
        nop
        andi    r4,r0,ICFG_SPDIF_ENA
        tsti    r4,ICFG_SPDIF_ENA               // check SPDIF flag
        bne     4f

        andi    r4,r0,ICFG_CLK_CHIP
        mupi    r3,Reg298_PCM_up

        tsti    r1,SAMPLING_FREQ_320
        bne     1f
        movi    r1,Reg284PCM320_SP
        tsti    r4,CH9081_2PIN
        bne     Lnot_9081_020
        mupi    r0,Reg350PCM320_up_SP_9081
        ori     r0,Reg350PCM320_dn_SP_9081
        j       Lnot_9081_022
Lnot_9081_020:
        mupi    r0,Reg350PCM320_up_SP_2
        ori     r0,Reg350PCM320_dn_SP_2
        tsti    r4,MK2744_2PIN
        beq     Lnot_9081_022
        mupi    r0,Reg350PCM320_up_SP_3
        ori     r0,Reg350PCM320_dn_SP_3
Lnot_9081_022:
        ori     r3,Reg298_320_dn
        j       3f
1:
        tsti    r1,SAMPLING_FREQ_441
        bne     2f
        movi    r1,Reg284PCM441_SP
        tsti    r4,CH9081_2PIN
        bne     Lnot_9081_030
        mupi    r0,Reg350PCM441_up_SP_9081
        ori     r0,Reg350PCM441_dn_SP_9081
        j       Lnot_9081_032
Lnot_9081_030:
        mupi    r0,Reg350PCM441_up_SP_2
        ori     r0,Reg350PCM441_dn_SP_2
        tsti    r4,MK2744_2PIN
        beq     Lnot_9081_032
        mupi    r0,Reg350PCM441_up_SP_3
        ori     r0,Reg350PCM441_dn_SP_3
Lnot_9081_032:
        ori     r3,Reg298_441_dn
        j       3f
2:
        tsti    r1,SAMPLING_FREQ_480
	bne	modify_sampling_freq_done
        movi    r1,Reg284PCM480_SP
        tsti    r4,CH9081_2PIN
        bne     Lnot_9081_040
        mupi    r0,Reg350PCM480_up_SP_9081
        ori     r0,Reg350PCM480_dn_SP_9081
        j       Lnot_9081_042
Lnot_9081_040:
        mupi    r0,Reg350PCM480_up_SP_2
        ori     r0,Reg350PCM480_dn_SP_2
        tsti    r4,MK2744_2PIN
        beq     Lnot_9081_042
        mupi    r0,Reg350PCM480_up_SP_3
        ori     r0,Reg350PCM480_dn_SP_3
Lnot_9081_042:
        ori     r3,Reg298_480_dn
3:
;        rswi    r3,SPDIF_channel_status
        mupi    r2,0x0001
        ori     r2,0x0100
        or      r1,r2                   // enable SPDIF, disable LRCK
        j       modify_sampling_freq
4:

        andi    r4,r0,ICFG_CLK_CHIP

        tsti    r1,SAMPLING_FREQ_320
        bne     1f
        movi    r1,Reg284PCM320
        tsti    r4,CH9081_2PIN
        bne     Lnot_9081_050
        mupi    r0,Reg350PCM320_up_9081
        ori     r0,Reg350PCM320_dn_9081
        j       Lnot_9081_052
Lnot_9081_050:
        mupi    r0,Reg350PCM320_up_2
        ori     r0,Reg350PCM320_dn_2
        tsti    r4,MK2744_2PIN
        beq     Lnot_9081_052
        mupi    r0,Reg350PCM320_up_3
        ori     r0,Reg350PCM320_dn_3
Lnot_9081_052:
        j       modify_sampling_freq
1:
        tsti    r1,SAMPLING_FREQ_441
        bne     2f
        movi    r1,Reg284PCM441
        tsti    r4,CH9081_2PIN
        bne     Lnot_9081_060
        mupi    r0,Reg350PCM441_up_9081
        ori     r0,Reg350PCM441_dn_9081
        j       Lnot_9081_062
Lnot_9081_060:
        mupi    r0,Reg350PCM441_up_2
        ori     r0,Reg350PCM441_dn_2
        tsti    r4,MK2744_2PIN
        beq     Lnot_9081_062
        mupi    r0,Reg350PCM441_up_3
        ori     r0,Reg350PCM441_dn_3
Lnot_9081_062:
        j       modify_sampling_freq
2:
        tsti    r1,SAMPLING_FREQ_480
	bne	modify_sampling_freq_done
        movi    r1,Reg284PCM480
        tsti    r4,CH9081_2PIN
        bne     Lnot_9081_070
        mupi    r0,Reg350PCM480_up_9081
        ori     r0,Reg350PCM480_dn_9081
        j       Lnot_9081_072
Lnot_9081_070:
        mupi    r0,Reg350PCM480_up_2
        ori     r0,Reg350PCM480_dn_2
        tsti    r4,MK2744_2PIN
        beq     Lnot_9081_072
        mupi    r0,Reg350PCM480_up_3
        ori     r0,Reg350PCM480_dn_3
Lnot_9081_072:

modify_sampling_freq:

        rlwi    r3,MicroClockCtrl       // load register 350
        mupi    r2,Reg350Clear_up_2
        ori     r2,Reg350Clear_dn_2
        tsti    r4,MK2744_3PIN
        bne     1f
        mupi    r2,Reg350Clear_up_3
        ori     r2,Reg350Clear_dn_3
1:
#ifdef	EFFECT
#ifndef	R3K_PCM_OUT_CTRL
	movi	r1,0x3c21		//same as PCM
	rswi    r1,PCM_Out_Ctrl
	li	r1,0x003800c7
	rswi    r1,MicroClockCtrl
#endif	// R3K_PCM_OUT_CTRL
#else	//EFFECT
#ifndef	R3K_PCM_OUT_CTRL
        rswi    r1,PCM_Out_Ctrl         // modify register 284
#endif	// R3K_PCM_OUT_CTRL
        and     r3,r2
        or      r3,r0
#ifndef	R3K_PCM_OUT_CTRL
        rswi    r3,MicroClockCtrl       // modify register 350
#endif	// R3K_PCM_OUT_CTRL
#endif	//EFFECT

#endif	// LS388
	
modify_sampling_freq_done:
//-------------------------------------------
#if !LS388
        dlw     r3,USER_ICFG
        nop
        andi    r3,ICFG_SPDIF_ENA
        tsti    r3,ICFG_SPDIF_ENA
        bne     1f
        dlw     r3,SPDIF_SET_FLAG
        nop
        tsti    r3,0x1
        beq     1f
        rlwi    r1,PCM_Out_Ctrl         // load register 284
        movi    r3,1
        dsw     r3,SPDIF_SET_FLAG
        mupi    r2,0x0001
        ori     r2,0x0100               // enable SPDIF, disable LRCK
        or      r1,r2                   // enable SPDIF, disable LRCK
#ifndef	R3K_PCM_OUT_CTRL
        rswi    r1,PCM_Out_Ctrl         // modify register 284
#endif	// R3K_PCM_OUT_CTRL
#endif	//LS388
1:
        movi    r8,0
        movh    LIcrc_error_count,r8
        movh    LItotal_error_count,r8
        movb    r8,LBhdr_error_protection
        tsti    r8,0
        bne     2f
        gbi     r8,16                   // CRC
        nop
        nop
        movh    LIold_crc,r8
2:      movb    r8,LBhdr_lay		/* <=>  switch (info.lay) */
        tsti    r8,1
        bne     chk_layer2
        movi    r8,32
        movb    LBbitsPerSlot,r8
        movi    r8,384
        movh    LIsamplesPerFrame,r8
        jsr     r26,SUB_I_decode_bitalloc
rtn_I_decode_bitalloc:

        jsr     r26,SUB_I_decode_scale
rtn_I_decode_scale:

        movb    r8,LBhdr_error_protection
        tsti    r8,0
        bne     end_I_chk_CRC
        jsr     r26,SUB_I_CRC_calc
rtn_I_CRC_calc:

        jsr     r26,SUB_chk_CRC
rtn_I_chk_CRC:

        tsti    r10,0
        bne     error_handler
end_I_chk_CRC:

        /* for (i=0;i<SCALE_BLOCK;i++) { ... } */
        movi    r6,0
        movb    LBblknum,r6
I_block_loop_start:
.if SB_OUT
        movi    AGRAdr4,local_sample_byte       // r5=addr. of sample[0][0][i]
        movi    r10,0
        mupi    r10,0x1111
        CLR_TrapReg
        loop    2,6f            // for(j=0;j<2;j++)
        loop    3,6f            // for(k=0;k<3;k++)
        loop    32,6f           // for(i=0;i<SBLIMIT;i++)
        mov     a4(4),r10
6:
        SET_TrapReg
.endif
        jsr     r26,SUB_I_buffer_sample
rtn_I_buffer_sample:

.if SB_OUT
        movi    r10,local_sample_byte
        rswi    r10,0x500       // start address to dump
        addi    r10,2*3*32*4
        rswi    r10,0x504       // end address to dump
        movi    r10,1
        rswi    r10,0x508       // enable dumping
.endif

#if NO_RHDEBUG
        jsr     r26,SUB_I_dequantize_sample
rtn_I_dequantize_sample:
123

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