app_mem.h

关于DVD的MPEG2用的DSP代码,在DSP的实现MPEG的压缩,解压算法.

// memory segment 
#if 	SVCD
#define DSP_START_SEG	0x9
#else	// !SVCD
#define DSP_START_SEG	0x10
#endif	// SVCD
#define	DSP_TEXT_SEG	(DSP_START_SEG+0)
#define DSP_DATA_SEG	(DSP_START_SEG+0)	// DataSeg (stereo_user.h)
#define DSP_SDATA_SEG	(DSP_START_SEG+1)	// MEM_SEG (user*.h)
#if SVCD
#define APP_TEXT_SEG	(DSP_START_SEG+1)
#define APP_DATA_SEG	(DSP_START_SEG+1)
#else
#define APP_TEXT_SEG	(DSP_START_SEG+2)
#define APP_DATA_SEG	(DSP_START_SEG+2)
#endif
#define SWITCH_DATA_SEG	(DSP_DATA_SEG!=APP_DATA_SEG)
//Local memory:
#define	LB_DcacheBase_temp	0x5c9
#define LB_APP_status	0x5c9
#define LB_APP_flag	0x5c9	

// DRAM memory:	use segement 0x10 MemSeg
// 0xff50, 0xff54, 0xff5c
#if SVCD
#define APP_COMM_BASE	0xd900
#else
#define APP_COMM_BASE	0x0000
#endif
/*
#define	APP_COMMAND		(APP_COMM_BASE+0x0)
#define	APP_STATUS		(APP_COMM_BASE+0x4)
#define APP_MISC		(APP_COMM_BASE+0x8)
#define APP_DEBUG		(APP_COMM_BASE+0xC)
#define PSM_DATA_PTR		(APP_COMM_BASE+0x10)
#define FRAME_COUNT_PTR		(APP_COMM_BASE+0x14)
#define EQUALIZER_DATA_PTR	(APP_COMM_BASE+0x18)
#define SOUND_EFFECT_FLAG	(APP_COMM_BASE+0x1C)
#define	RISC_FLAG1			(APP_COMM_BASE+0x20)
#define	RISC_FLAG2			(APP_COMM_BASE+0x24)
#define	RISC_FLAG3			(APP_COMM_BASE+0x28)
#define MP3_DATA_PTR		(APP_COMM_BASE+0x2c)
*/
#define	APP_CMD_NOP		0x0
#define	APP_CMD_UNKOWN	0xff

#define APP_CMD_PSM				0x40
#define APP_CMD_PSM_DISABLE		(APP_CMD_PSM+0)
#define APP_CMD_PSM_ENABLE		(APP_CMD_PSM+1)
#define APP_CMD_EQU_DISABLE		(APP_CMD_PSM+2)
#define APP_CMD_EQU_ENABLE		(APP_CMD_PSM+3)
#define APP_CMD_EQU_COEFF		(APP_CMD_PSM+4)

#define APP_CMD_RR				0x50
#define APP_CMD_RR_DISABLE		(APP_CMD_RR+0)
#define APP_CMD_RR_ENABLE		(APP_CMD_RR+1)
#define APP_CMD_RR_MODE_RESING	(APP_CMD_RR+2)
#define APP_CMD_RR_MODE_REREAD	(APP_CMD_RR+3)

#define	APP_CMD_RR_REC_STOP		(APP_CMD_RR+4)
#define	APP_CMD_RR_REC_RUN		(APP_CMD_RR+5)
#define	APP_CMD_RR_PLAY_STOP	(APP_CMD_RR+6)
#define	APP_CMD_RR_PLAY_RUN		(APP_CMD_RR+7)


/*
#define	APP_CMD_RR_REC		0x54
#define	APP_CMD_RR_PLAY		0x55
#define	APP_CMD_RR_STOP		0x56
#define	APP_CMD_RR_RUN		0x57
*/
#define APP_CMD_ACK		0x100

#define APP_PSM_ENABLE		0x20	// (0x1<<5)
#define APP_PSM_RUN			0x01
#define APP_PSM_STOP		0xFE
#define APP_EQU_RUN			0x02
#define APP_EQU_STOP		0xFD

#define APP_RR_ENABLE		0x40	// (0x2<<5)
/*
#define APP_RR_RUN			0x01
#define APP_RR_STOP			0xFE
#define APP_RR_PLAY			0x02
#define APP_RR_REC			0xFD
*/

#define APP_RR_REC_RUN		0x01
#define APP_RR_REC_STOP		0xFE
#define APP_RR_PLAY_RUN		0x02
#define APP_RR_PLAY_STOP	0xFD

#define APP_RR_MODE_REREAD	0x04
#define APP_RR_MODE_RESING	0xFB
#define APP_RR_STATUS0		0x08
#define APP_RR_STATUS1		0x10

		.macro	SWITCH_TO_DSP
#if SWITCH_DATA_SEG
	movi	DcacheBase, DSP_DATA_SEG
	nop
#endif	
	.endm
	
	.macro	SWITCH_TO_APP
#if SWITCH_DATA_SEG
	movi	DcacheBase, APP_DATA_SEG
	nop
#endif	
	.endm

	.macro INCW	REG, ADDRESS
	dlw	\REG, \ADDRESS
	nop
	addi \REG, 1
	dsw	\REG, \ADDRESS
	.endm

	.macro INCB	REG, ADDRESS
	dlb	\REG, \ADDRESS
	nop
	addi \REG, 1
	dsb	\REG, \ADDRESS
	nop
	nop
	.endm

#if !SVCD
	.macro	DMAwr	REG
	shl	\REG,2
	mov	DmaByteWr,\REG
        shr     \REG,2
	.endm

	.macro	DMArr	REG
	shl	\REG,2
	mov	DmaByteRd,\REG
        shr     \REG,2
	.endm
#endif