📄 user.h
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//---------------------------------------
#define Reg350Mask 0x737300
#else // CERTIFYBOARD
//---------------------------------------
// Regular board:
// 1. 2-Pin MK2744 2. 3-Pin MK2744 3. 2-Pin CH9081
// AS2 - GIO5 GIO3 --
// AS1 - GIO5 GIO5 GIO5
// AS0 - GIO4 GIO4 GIO4
//---------------------------------------
#define Reg350Mask_up_2 0x0030
#define Reg350Mask_dn_2 0x3000
#define Reg350Clear_up_2 0xffcf
#define Reg350Clear_dn_2 0xcfff
#define Reg350Mask_up_3 0x0038
#define Reg350Mask_dn_3 0x3800
#define Reg350Clear_up_3 0xffc7
#define Reg350Clear_dn_3 0xc7ff
#ifdef I2S
#if SR48
#define Reg350PCM320_up_2_48 0x0030
#define Reg350PCM320_dn_2_48 0x2000
#define Reg350PCM441_up_2_48 0x0030
#define Reg350PCM441_dn_2_48 0x2000 //this has to be corercted with 3rd GPIO
#define Reg350PCM480_up_2_48 0x0030
#define Reg350PCM480_dn_2_48 0x2000
#define Reg350PCM320_up_3_48 0x0038
#define Reg350PCM320_dn_3_48 0x2800
#define Reg350PCM441_up_3_48 0x0038
#define Reg350PCM441_dn_3_48 0x2800 //this has to be corercted with 3rd GPIO
#define Reg350PCM480_up_3_48 0x0038
#define Reg350PCM480_dn_3_48 0x2800
#endif // SR48
#define Reg284PCM320 0x0eff
#define Reg284PCM441 0x0eff
#define Reg284PCM480 0x0eff
#define Reg350PCM320_up_2 0x0030
#define Reg350PCM320_dn_2 0x0000
#define Reg350PCM441_up_2 0x0030
#define Reg350PCM441_dn_2 0x2000 //this has to be corercted with 3rd GPIO
#define Reg350PCM480_up_2 0x0030
#define Reg350PCM480_dn_2 0x2000
#define Reg350PCM320_up_3 0x0038
#define Reg350PCM320_dn_3 0x0000
#define Reg350PCM441_up_3 0x0038
#define Reg350PCM441_dn_3 0x2800 //this has to be corercted with 3rd GPIO
#define Reg350PCM480_up_3 0x0038
#define Reg350PCM480_dn_3 0x2800
#ifdef CH9081
#define Reg350PCM320_up_9081 0x0030
#define Reg350PCM320_dn_9081 0x2000
#define Reg350PCM441_up_9081 0x0030
#define Reg350PCM441_dn_9081 0x2000
#define Reg350PCM480_up_9081 0x0030
#define Reg350PCM480_dn_9081 0x2000
#endif // CH9081
#else // I2S
#if SR48
#define Reg284PCM320 0x0825
#define Reg284PCM441 0x0825
#define Reg284PCM480 0x0825
#define Reg350PCM320_up_2 0x0030
#define Reg350PCM320_dn_2 0x0000
#define Reg350PCM441_up_2 0x0030
#define Reg350PCM441_dn_2 0x0000
#define Reg350PCM480_up_2 0x0030
#define Reg350PCM480_dn_2 0x0000
#define Reg350PCM320_up_3 0x0038
#define Reg350PCM320_dn_3 0x0000
#define Reg350PCM441_up_3 0x0038
#define Reg350PCM441_dn_3 0x0000
#define Reg350PCM480_up_3 0x0038
#define Reg350PCM480_dn_3 0x0000
#ifdef CH9081
#define Reg350PCM320_up_9081 0x0030
#define Reg350PCM320_dn_9081 0x2000
#define Reg350PCM441_up_9081 0x0030
#define Reg350PCM441_dn_9081 0x2000
#define Reg350PCM480_up_9081 0x0030
#define Reg350PCM480_dn_9081 0x2000
#endif // CH9081
#else // SR48
#define Reg284PCM320 0x0c65
#define Reg284PCM441 0x0c25
#define Reg284PCM480 0x0c25
#define Reg350PCM320_up_2 0x0030
#define Reg350PCM320_dn_2 0x0000
#define Reg350PCM441_up_2 0x0030
#define Reg350PCM441_dn_2 0x1000
#define Reg350PCM480_up_2 0x0030
#define Reg350PCM480_dn_2 0x0000
#define Reg350PCM320_up_3 0x0038
#define Reg350PCM320_dn_3 0x0000
#define Reg350PCM441_up_3 0x0038
#define Reg350PCM441_dn_3 0x1000
#define Reg350PCM480_up_3 0x0038
#define Reg350PCM480_dn_3 0x0000
#ifdef CH9081
#define Reg350PCM320_up_9081 0x0030
#define Reg350PCM320_dn_9081 0x0000
#define Reg350PCM441_up_9081 0x0030
#define Reg350PCM441_dn_9081 0x1000
#define Reg350PCM480_up_9081 0x0030
#define Reg350PCM480_dn_9081 0x2000
#endif // CH9081
#endif // SR48
#endif // I2S
#endif // CERTIFYBOARD
#if LS388
#define LS500_ID 0x00000000
#define LS508_ID 0x00000200 // LS500B, LS500C, LS508, LS1888
#define PLL_CTRL_48K_500 0x48AB1000
#define PLL_DIV_48K_500 0x46
#define PLL_CTRL_441K_500 0x0D0B1000
#define PLL_DIV_441K_500 0x15A
#define PLL_CTRL_48K_508 0x000108ab
#define PLL_DIV_48K_508 0x01110000
#define PLL_CTRL_441K_508 0x00000d0b
#define PLL_DIV_441K_508 0x01560000
#define PLL_CTRL_441K_1888 0x0310007d
#define PLL_CTRL_48K_1888 0x0200004b
#define CHANNEL_STATUS_48K 0x02000040
#define CHANNEL_STATUS_441K 0x02000000
#endif // LS388
#define PCM_FIFO_BASE 0
#define PCM_FIFO_0_START PCM_FIFO_BASE
#define PCM_FIFO_0_END PCM_FIFO_0_START+255*6*4
#define PCM_FIFO_1_START PCM_FIFO_BASE+256*6*4
#define PCM_FIFO_1_END PCM_FIFO_1_START+255*6*4
#define PCM_FIFO_SIZE PCM_FIFO_1_END-PCM_FIFO_0_START
// location of PCM_FIFO in main memory
#ifdef EFFECT
#define PCM_OUT_START 0
#define PCM_OUT_END 0x3000 // 0x1800
#endif // EFFECT
#ifdef I2S // 1 sample per 32-bit word
#define PCM_FIFO_BASE 0
#if SR48
#define PCM_STORE_SIZE 40*8
//#define PCM_FIFO_BASE 0 //moved out
#define PCM_FIFO_SIZE 0xbff
#define PCM_FIFO_0_START PCM_FIFO_BASE
#define PCM_FIFO_1_END PCM_FIFO_0_START+PCM_FIFO_SIZE+1
#endif // SR48
#define PCM_FIFO_BASE_44 0
#define PCM_FIFO_0_START_44 PCM_FIFO_BASE_44
#define PCM_FIFO_0_END_44 PCM_FIFO_0_START_44+(32*3*2-1)*4
#define PCM_FIFO_1_START_44 PCM_FIFO_BASE_44+32*3*2*4
#define PCM_FIFO_1_END_44 PCM_FIFO_1_START_44+(32*3*2-1)*4
#define PCM_FIFO_SIZE_44 0x5ff
#else // I2S
#if SR48
#define PCM_STORE_SIZE 40*4
//#define PCM_FIFO_BASE 0 //moved out
#define PCM_FIFO_SIZE 0x5ff
#define PCM_FIFO_0_START PCM_FIFO_BASE
#define PCM_FIFO_1_END PCM_FIFO_0_START+PCM_FIFO_SIZE+1
#endif // SR48
#define PCM_FIFO_BASE_44 0
#define PCM_FIFO_0_START_44 PCM_FIFO_BASE_44
#define PCM_FIFO_0_END_44 PCM_FIFO_0_START_44+(32*3-1)*4
#define PCM_FIFO_1_START_44 PCM_FIFO_BASE_44+32*3*4
#define PCM_FIFO_1_END_44 PCM_FIFO_1_START_44+(32*3-1)*4
#define PCM_FIFO_SIZE_44 0x2ff
#endif // I2S
#if SPDIF_OUT
#define PCM_FIFO_BASE_SP 0
#define PCM_FIFO_0_START_SP PCM_FIFO_BASE_SP
#define PCM_FIFO_0_END_SP PCM_FIFO_0_START_SP+(32*3-1)*4
#define PCM_FIFO_1_START_SP PCM_FIFO_BASE_SP+32*3*4
#define PCM_FIFO_1_END_SP PCM_FIFO_1_START_SP+(32*3-1)*4
#define PCM_FIFO_SIZE_SP 0x2ff
#define Reg298_PCM_up 0x0200
#define Reg298_AC3_up 0x4099
#define Reg298_320_dn 0x0060
#define Reg298_441_dn 0x0000
#define Reg298_480_dn 0x0040
//xxx 1-7-98 #define Reg284PCM320_SP 0x0c65
//xxx 1-7-98 #define Reg284PCM441_SP 0x0c25
//xxx 1-7-98 #define Reg284PCM480_SP 0x0c25
#define Reg284PCM320_SP 0x0265
#define Reg284PCM441_SP 0x0225
#define Reg284PCM480_SP 0x0225
#define Reg350PCM320_up_SP_2 0x0030
#define Reg350PCM320_dn_SP_2 0x0000
#define Reg350PCM441_up_SP_2 0x0030
#define Reg350PCM441_dn_SP_2 0x1000
//#define Reg350PCM441_dn_SP_2 0x1100
#define Reg350PCM480_up_SP_2 0x0030
#define Reg350PCM480_dn_SP_2 0x0000
#define Reg350PCM320_up_SP_3 0x0038
#define Reg350PCM320_dn_SP_3 0x0000
#define Reg350PCM441_up_SP_3 0x0038
#define Reg350PCM441_dn_SP_3 0x1000
//#define Reg350PCM441_dn_SP_3 0x1100
#define Reg350PCM480_up_SP_3 0x0038
#define Reg350PCM480_dn_SP_3 0x0000
#ifdef CH9081
#define Reg350PCM320_up_SP_9081 0x0030
#define Reg350PCM320_dn_SP_9081 0x0000
#define Reg350PCM441_up_SP_9081 0x0030
#define Reg350PCM441_dn_SP_9081 0x1000
#define Reg350PCM480_up_SP_9081 0x0030
#define Reg350PCM480_dn_SP_9081 0x2000
#endif // CH9081
#endif // SPDIF_OUT
#define ICFG_CLK_CHIP 0x7
#define ICFG_SPDIF_ENA 0x80
#define MK2744_2PIN 0x0
#define CH9081_2PIN 0x1
#define MK2744_3PIN 0x2
// Constants for AC-3 sync code, not used in MPEG
#define AC3I_ERR_SYNC 1
#define AC3I_ERR_DATARATE 3
#define AC3I_ERR_SAMPRATE 2
#define SYNC_WORD 0x770b
#define LIicfg %0x0
// Macro defined for LS220 work around
.MACRO CLR_TrapReg
#ifndef LS240
movi TrapReg,0
nop
nop
#endif
.ENDM
.MACRO CLR_TrapReg_1
#ifndef LS240
movi TrapReg,0
#endif
.ENDM
.MACRO SET_TrapReg
#ifndef LS240
movi TrapReg,1<<2
#endif
.ENDM
#define RegStrWrPtr 0x914>>2
#define RegStrRdPtr 0x918>>2
#define RegPTSWrPtr 0x91c>>2
#define RegPTSRdPtr 0x920>>2
#if 1 /* Use DRAM for Pointers */
.MACRO LdStrRdPtr RegRdPtr
dlw \RegRdPtr,Stream_Rd_Ptr
.ENDM
.MACRO LdStrWrPtr RegWrPtr
dlw \RegWrPtr,Stream_Wr_Ptr
.ENDM
.MACRO SvStrRdPtr RegRdPtr
dsw \RegRdPtr,Stream_Rd_Ptr
.ENDM
.MACRO SvStrWrPtr RegWrPtr
dsw \RegWrPtr,Stream_Wr_Ptr
.ENDM
.MACRO LdPTSRdPtr RegRdPtr
dlw \RegRdPtr,PTS_FIFO_Rd_Ptr
.ENDM
.MACRO LdPTSWrPtr RegWrPtr
dlw \RegWrPtr,PTS_FIFO_Wr_Ptr
.ENDM
.MACRO SvPTSRdPtr RegRdPtr
dsw \RegRdPtr,PTS_FIFO_Rd_Ptr
.ENDM
.MACRO SvPTSWrPtr RegWrPtr
dsw \RegWrPtr,PTS_FIFO_Wr_Ptr
.ENDM
#else /* Use Register for Pointers */
.MACRO LdStrRdPtr RegRdPtr
rlwi \RegRdPtr,RegStrRdPtr
.ENDM
.MACRO LdStrWrPtr RegWrPtr
rlwi \RegWrPtr,RegStrWrPtr
.ENDM
.MACRO SvStrRdPtr RegRdPtr
rswi \RegRdPtr,RegStrRdPtr
.ENDM
.MACRO SvStrWrPtr RegWrPtr
rswi \RegWrPtr,RegStrWrPtr
.ENDM
.MACRO LdPTSRdPtr RegRdPtr
rlwi \RegRdPtr,RegPTSRdPtr
.ENDM
.MACRO LdPTSWrPtr RegWrPtr
rlwi \RegWrPtr,RegPTSWrPtr
.ENDM
.MACRO SvPTSRdPtr RegRdPtr
rswi \RegRdPtr,RegPTSRdPtr
.ENDM
.MACRO SvPTSWrPtr RegWrPtr
rswi \RegWrPtr,RegPTSWrPtr
.ENDM
#endif
/* code ID */
#define DSP_HEX_ID 0x1818
/* PLL variables from RISC */
#define VAL_PLL_CTRL_44p1K 0x1824
#define VAL_PLL_CTRL_48K 0x1828
#define VAL_PLL_DIV_44p1K 0x1834
#define VAL_PLL_DIV_48K 0x1838
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