📄 user.h
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; Module: user
;
#ifdef EFFECT
// .extern OLD_Stream_Rd_Ptr
.extern Debug_Dump_Ptr
#endif
#define IBUF_SIZE 0x4000 // 2304 bytes
#define IBUF_START 0x8000 // 2304 byte
#define IBUF_SIZE_OVER_4 0X1000
#define IBUF_END_OVER_4 0X3000
#define IBUF_END IBUF_START+IBUF_SIZE // 3840 byte
#define IBUF_END_plus1 IBUF_START+IBUF_SIZE // 3840 byte
//#define MIN_IBUF_DEPTH 0x1000
#define MIN_IBUF_DEPTH 0x800
//#ifdef DB_FLAG
//#define DB_FLAG_ADR 0xe800 // 0xe010
#define DB_FLAG_ADR 0xef00 // ZhangWei:0xe800 is in the .data segment with code
//#endif
#define PTS_FIFO_START 0xfa00 // 2 elements(PTS,byte count) per entry
#define PTS_FIFO_END 0xfe00
#define PTS_FIFO_SIZE (PTS_FIFO_END-PTS_FIFO_START)
#define PTS_FIFO_ENTRY (PTS_FIFO_END-PTS_FIFO_START)>>3
// copy protection stuff
#define Drv_RD 0xfef0 // 5 byte
#define Drv_acc 0xfef8 // 1 byte 0xfef5
#define Drv_CD 0xfefc // 10 byte 0xfef6
//#define BUS_KEY0 0xff68
//#define BUS_KEY4 0xff6c
#define BUS_KEY0 0xf168 // 0xf168
#define BUS_KEY4 0xf16c // 0xf16c
#define USER_DATA 0xff74
#define VER_SCALE 0xff78
#define USER_ICFG 0xff7c
// USER_ICFG definition:
// Bits Definition
// 15: Microphone input enable
// 14: LS128?
// 13: Reverb bypass
// 12: Hardware echo chip
// 7: SPDIF enabled (1 - enabled, 0 - disabled)
// 6: I2S DAC (1 - I2S, 0 - non I2S)
// 5-4: PCM size (00 - 16 bit, 01 - 18 bit, 10 - 20 bit, 11 - 24 bit)
// 3: left channel polarity
// 2-0: clock chip (000 - MK2744/2-pin, 001 - CH9081/2-pin,
// 010 - MK2274/3-pin)
//------New flag about KarlaOK system--------------------
#define ICFG_HWECHO_MASK 0x1000 //1 = HW-ECHO, 0 = SW-ECHO
#define ICFG_REVERB_BYPASS_MASK 0x2000 //1 = bypass reverb, 0 = reverb
#define ICFG_LS128_MASK 0x4000 //1 = LS128, 0 = not LS128
#define ICFG_MIC_EXIST_MASK 0x8000 //1 = MIC exist, 0 = MIC not exist
//-------------------------------------------------------
#define USER_DATA 0xff74
#define VER_SCALE 0xff78
#define USER_OCFG 0xff80
#define SAMPLING_FREQ_320 0x2
#define SAMPLING_FREQ_441 0x0
#define SAMPLING_FREQ_480 0x1
//#define TRAPREG_VAL 0
#define TRAPREG_VAL 0x1<<2
#define SPDIF_SET_FLAG 0xff88
#define KARAOKE_0 0xff8c
#define KARAOKE_1 0xff90
#define PCM_SCALE 0xffb0
#define FILL_PATTERN 0xffbc
#ifdef CMD_BUF
#define CMD_BUF_ADR 0xffc0
#endif
#define PTS_FIFO_Start 0xffd0
#define PTS_FIFO_End 0xffd4
#define PTS_FIFO_Wr_Ptr 0xffd8
#define PTS_FIFO_Rd_Ptr 0xffdc
#ifdef STREAM_SIM
#define MEM_SEG 0
#define Stream_Enable 0x104
#define Stream_Start 0x108
#define Stream_Size 0x10c
#define Stream_Rd_Ptr 0x110
#else
#ifdef LS388
#if SVCD
#define MEM_SEG 0x9
#else // SVCD
#define MEM_SEG 0x10
#endif // SVCD
//#define Comm_Reg0 0x10>>2
//#define Comm_Reg1 0x14>>2
//#define Comm_Reg2 0x18>>2
//#define Comm_Reg3 0x1c>>2
#define Comm_Reg3 (0x10c>>2)
//#define Comm_Reg3 (0xd08>>2)
#else // LS388
#define MEM_SEG 0x1f
#endif // LS388
#define Stream_Start 0xffe0
#define Stream_End 0xffe4
#define Stream_Wr_Ptr 0xffe8
#define Stream_Rd_Ptr 0xffec
#endif // STREAM_SIM
#ifdef STREAM_SIM
#define PCM_Rd_Ptr 0x294
#else // STREAM_SIM
#ifdef FILE_OUT
#define PCM_Rd_Ptr 0xffd8
#else // FILE_OUT
#ifdef LS388
#define PCM_Rd_Ptr (0xe14>>2)
#define SPDIF_channel_status (0xe18>>2)
#else // LS388
#define PCM_Rd_Ptr (0x294>>2)
#define SPDIF_channel_status (0x298>>2)
#endif // LS388
#endif // FILE_OUT
#endif // STREAM_SIM
#define COMMAND0 0xfff0
#define COMMAND1 0xfff4
#define STATUS0 0xfff8
#define STATUS1 0xfffc
// executive host command
#define CMD_NOP 0x0
#define CMD_AC3 0x80
#define CMD_MPEG1 0x81
#define CMD_MPEG2 0x82
#define CMD_PCM 0x83
#define CMD_PLAY 0x84
#define CMD_STOPF 0x85
#define CMD_STOP 0x86 // PAUSE in host side
#define CMD_STOPB 0x87
#define CMD_UNMUTE 0x88
#define CMD_CONFIG 0x89
#define CMD_VER 0x8a
#define CMD_STAT 0x8b
#define CMD_GAIN 0x8c
#define CMD_SPDIF 0x8d
//#define CMD_FIELD_LOCK 0x8e
#define CMD_EOD 0x8e
#define CMD_FRAMES 0xa0
#define CMD_CPYP_CLEAR 0xa1
#define CMD_CPYP_DEC_AUTH 0xa2
#define CMD_CPYP_DRV_AUTH 0xa3
#define CMD_CPYP_KEY_SHARE 0xa4
#define CMD_CPYP_DISC_KEY 0xa5
#define CMD_CPYP_TITLE_KEY 0xa6
#define CMD_CPYP_SET_TK 0xa7
#define CMD_CPYP_DRIVER_TYPE 0xa8
#define CMD_SLOW_PLAY 0xb1
#define CMD_FAST_PLAY 0xb2
#define CMD_FF_FB_PLAY 0xb3
#define CMD_STEP_PLAY 0xb4
#define CMD_PAUSE_RESUME 0xb5
#define CMD_FORCE_DISPLAY 0xb6
#define CMD_NORMAL_PLAY 0xb7
#define CMD_SKIP_TO_I_FRAME 0xb8
#define CMD_FIELD_LOCK_ON 0xb9
#define CMD_FIELD_LOCK_OFF 0xba
#define CMD_NEW_AV_DELTA 0xbb
#define CMD1_QSOUND 0x800
#define CMD1_QSOUND_A 0x802 // QSurround with attenuation
#define CMD1_QSOUND_OFF 0x801
#define CMD1_AVF 0xa00
#define CMD1_AVF_OFF 0xa10
#define CMD1_AVF_L_ON 0xa01
#define CMD1_AVF_L_OFF 0xa11
#define CMD1_AVF_R_ON 0xa02
#define CMD1_AVF_R_OFF 0xa12
#define CMD1_AVF_LR_ON 0xa03
#define CMD1_AVF_LR_OFF 0xa13
#define ERROR_MASK 0xf // bit 3..0
#define RUN_STOP_MASK 0x10 // bit 4
#define MUTE_MASK 0x20 // bit 5
#define PROCESSOR_MASK 0x700 // bit 10..8
#define FIRST_PCM_OUT 0x800 // bit 11
#define PAUSE 0x1000 // bit 12
#define NEW_OLD_MASK 0x4000 // bit 14
#define SYSINIT_MASK 0x8000 // bit 15
#define NO_SYNC_ERROR 0xfffe
//#define ROM_VER 0x100
//---------------------------------------------------------
// ROM_VER identification
// bit 8-11 = 1 for AC-3 and PCM, 2 for MPEG-1, 3 for MPEG-2
// bit 6-7 = 0 CLK SEL not supported, 1 CLK SEL supported
// bit 4-5 = 0 for non I2S, 1 for I2S
// bit 0-3 = 0 no SPDIF out, 1 with SPDIF out
#ifdef CH9081
#ifdef MPEG_2
#ifdef I2S
#if SPDIF_OUT
#define ROM_VER 0x351
#else // SPDIF_OUT
#define ROM_VER 0x350
#endif // SPDIF_OUT
#else // I2S
#if SPDIF_OUT
#define ROM_VER 0x341
#else // SPDIF_OUT
#define ROM_VER 0x340
#endif // SPDIF_OUT
#endif // I2S
#else // MPEG_2
#ifdef I2S
#if SPDIF_OUT
#define ROM_VER 0x251
#else // SPDIF_OUT
#define ROM_VER 0x250
#endif // SPDIF_OUT
#else // I2S
#if SPDIF_OUT
#define ROM_VER 0x241
#else // SPDIF_OUT
#define ROM_VER 0x240
#endif // SPDIF_OUT
#endif // I2S
#endif // MPEG_2
#else // CH9081
#ifdef MPEG_2
#ifdef I2S
#if SPDIF_OUT
#define ROM_VER 0x311
#else // SPDIF_OUT
#define ROM_VER 0x310
#endif // SPDIF_OUT
#else // I2S
#if SPDIF_OUT
#define ROM_VER 0x301
#else // SPDIF_OUT
#define ROM_VER 0x300
#endif // SPDIF_OUT
#endif // I2S
#else // MPEG_2
#ifdef I2S
#if SPDIF_OUT
#define ROM_VER 0x211
#else // SPDIF_OUT
#define ROM_VER 0x210
#endif // SPDIF_OUT
#else // I2S
#if SPDIF_OUT
#define ROM_VER 0x201
#else // SPDIF_OUT
#define ROM_VER 0x200
#endif // SPDIF_OUT
#endif // I2S
#endif // MPEG_2
#endif // CH9081
//---------------------------------------------------------
#define STATUS_STOP 0x0
#define PROCESS_OLD 0x0
#define RESET_ERROR 0xfff0
#define RESET_ERR_SYNC 0xfffe
#define RESET_STOP 0xffef
#define SET_RUN 0x10
#define SET_MUTE 0x20
#define RESET_UNMUTE 0xffdf
#define SET_SYSINIT 0x8000 // set bit 15 to 1
#define RESET_SYSINIT 0x7fff
#define SET_PROCESS_NEW 0x4000 // set bit 14 to 1
#define RESET_PROCESS_OLD 0xbfff // set bit 14 to 0
#define SET_PAUSE 0x1000
#define RESET_RESUME 0xefff
#ifdef CERTIFY
#define RESET_STOP_IDLE 0xfdee
#endif
/* PCM FIFO parameter */
#ifdef LS388
#define Chip_Id (0x04>>2)
#define Audio_CtrlReg (0x700>>2)
#define PCM_Run_Halt (0xe00>>2)
#define PCM_Out_Ctrl (0xe04>>2)
#define PCM_FIFO_StartReg (0xe08>>2)
#define PCM_FIFO_EndReg (0xe0c>>2)
#define PCM_In_Control_Reg (0xe20>>2)
#define PCM_In_Fifo_Start_Addr (0xe24>>2)
#define PCM_In_Fifo_End_Addr (0xe28>>2)
#define PCM_In_Current_Addr (0xe38>>2)
#define MicroClockCtrl (0x44>>2)
#define PLL_Ctrl_Reg1 (0xf0>>2)
#define PLL_Ctrl_Reg2 (0xf4>>2)
#define PLL_Off_Reg (0xf8>>2)
#define PLL_Clk_Div_Reg (0xfc>>2)
#else //LS388
#define Audio_CtrlReg (0x200>>2)
#define PCM_Run_Halt (0x280>>2)
#define PCM_Out_Ctrl (0x284>>2)
#define PCM_FIFO_StartReg (0x288>>2)
#define PCM_FIFO_EndReg (0x28c>>2)
#define MicroClockCtrl (0x350>>2)
#endif //LS388
#ifdef CERTIFYBOARD
//---------------------------------------
// Certification board: GIO6 -AS2;
// GIO5 -AS1;
// GIO4 -AS0;
// GIO1 -FC1;
// GIO0 -FC0
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