pcm_out.s

关于DVD的MPEG2用的DSP代码,在DSP的实现MPEG的压缩,解压算法.

        and     r8, r1                  //keep only 16-bit data
	or	a0(1*4), r6, r8		//put back 32-bit pair
Lpcm_gain_loop_3:
        j       Lend_of_gain_loop
Lr_to_lr_sp:
        loop    96, Lpcm_gain_loop_2
	and	r3, r1, a0(0*4)		//get upper 16-bit
	shra	r3, 8			//sign-extented to 1.23 format
	mulf	r6, r4, r3
        nop
	rnd	r6
        nop
        nop
        nop
        shr     r8, r6, 8               //align to lower 16-bit
	and	r8, r0			//keep only 16-bit data
	shl	r6, 8			//align to upper 16-bit; pipeline
	and	r6, r1			//keep only 16-bit data
	or	a0(1*4), r6, r8		//put back 32-bit pair
Lpcm_gain_loop_2:
        j       Lend_of_gain_loop
Ll_to_lr_sp:
        loop    96, Lpcm_gain_loop_1
        and     r3, r0, a0(0*4)         //get lower 16-bit
        shl     r3, 8
	shra	r3, 8			//sign-extented to 1.23 format
	mulf	r6, r4, r3
        nop
	rnd	r6
        nop
        nop
        nop
        shr     r8, r6, 8               //align to lower 16-bit
	and	r8, r0			//keep only 16-bit data
	shl	r6, 8			//align to upper 16-bit; pipeline
	and	r6, r1			//keep only 16-bit data
	or	a0(1*4), r6, r8		//put back 32-bit pair
Lpcm_gain_loop_1:
Lend_of_gain_loop:
        SET_TrapReg

	
        // DMA scaled sample to FIFO
	movi	r3, local_pcm_sample_word	; word addr
	shr	r9, r10, 2		; to word addr
        CLR_TrapReg
	loop	3, write_pcm_buf	;total of 32*3 words
	mov	LocalAddr, r3	
	dmawr	r9			;r10=FPApcmbufptr[outchan]=pcmptr2(init)
wait_dma_21:
	mov	r2,StatusPort
	tsti	r2,DmaDoneBit
	bz	wait_dma_21		;wait for dma done
	addi	r3, 32			;32 words each block
	addi	r9, 32
write_pcm_buf:
        SET_TrapReg
		
        movi    r9, PCM_FIFO_1_START_SP
        tsti    r10, PCM_FIFO_0_START_SP
	beq	toggle_FIFO_ptr
        movi    r9, PCM_FIFO_0_START_SP
toggle_FIFO_ptr:
	movh	LIFIFO_BLK_PTR, r9	;toggle block ptr 

	movi	r1, 1
	movb	LBPCM_flag, r1		;set the flag
pcm_not_out:
.endif // PCM_OUT
	j	r26
#endif // SPDIF_OUT
        //------------ End of Out_fifo_spdif --------------


;************************************************************************
; (c)1996-1997 Copyright M-Pact, Inc. All rights reserved
;
; Revision 1.0
;
;	
;
;	Module: SUB_SubBandSynthesis
;
;	Initial version:Jinshi Huang 4/1/97
;
;	Calling	:     	SUB_out_fifo
;	Called by:	Main
;	Return:		r26
;	Param in:     	
;	Temp reg:	
;	AGR  reg:	
;	Local buffer:
;************************************************************************
	.nolist
#include "regdef.h"
#include "memory.h"
#include "constant.h"
	.list

	
	.text
	.global	SUB_out_fifo
	
SUB_out_fifo:
#ifdef	I2S
#if SPDIF_OUT
        dlw     r0,USER_ICFG
        nop
        andi    r0,ICFG_SPDIF_ENA
        tsti    r0,ICFG_SPDIF_ENA
        beq     Out_fifo_spdif
#endif
#endif
	movb	r0, LBhdr_lay
	tsti	r0, 1
	bgt	output_3_blocks_44	//if layer_II, output now
	movb	r0, LBout_blk	//if layer_I, accumulate 3 blocks
	tsti	r0, 3
	beq	Layer_I_out_44
	movi	r1, 1
	movb	LBPCM_flag, r1		;set the flag so that main loop
					//can continue
	j	r26		//return without output
Layer_I_out_44:
output_3_blocks_44:
.if     PCM_OUT
	movb	r1, LBFIFO_flag
	movb	r4, LBblknum
	tsti	r1, 0
	beq	no_checking_FIFO_44
	movh	r10, LIFIFO_BLK_PTR
	movi	r8, PCM_FIFO_0_START_44	;  beginning of FIFO_0
	movi	r9, PCM_FIFO_0_END_44	;  to the end of FIFO being read
	tsti	r10, PCM_FIFO_0_START_44
	beq	toggle_ref_ptr_44
	movi	r8, PCM_FIFO_1_START_44	; beginning of FIFO_1
	movi	r9, PCM_FIFO_1_END_44	; end of FIFO_1
toggle_ref_ptr_44:
		
        ;; read location of read fifo
pcmout_wait_44:	
#ifdef        FILE_OUT
      dlw     r1,PCM_Rd_Ptr   ; read current pointer assigned by host
      nop
#else
	rlwi	r1, PCM_Rd_Ptr	; read current pointer register (28c)
#endif
#ifdef STREAM_SIM
	shr	r1, 16		; make it just the current address portion
#else
	andi	r1,0xffff
#endif
	tst	r1, r8
	blt	write_to_FIFO_44
	
	tst	r1, r9		; 
	blte	pcm_not_out_44	; if begin <= ptr <= end, wait
		
	j	write_to_FIFO_44

        // write to the FIFO
        ;====write 3*32 words to main memory. 
        ;this is modified to write 16-bit format of 2 channels to
        ;0 - 0x300 of the DRAM which is the PCM output FIFO.
no_checking_FIFO_44:
	movb	r0, LBhdr_lay
	tsti	r0, 1
	bgt	layer_II_fifo_44	//if layer_II, check block 0
	tsti	r4, 2		//if layer_I, check block 2
	bne	second_FIFO_block_44
	j continue_fifo_44
layer_II_fifo_44:				
	tsti	r4, 0
	bne	second_FIFO_block_44
continue_fifo_44:	
        ;;; set the size of the PCM output FIFO for 2 blocks
	movi	r1, PCM_FIFO_SIZE_44	; size of PCM output FIFO
#ifdef STREAM_SIM
				; 28c is PCM FIFO end address in real chip
				; and should contain full address,seg+offset
				; will be set by host for the time being.
	rswi	r1, 0x28c	; write to register
#endif
	movi	r10, PCM_FIFO_0_START_44
	j	write_to_FIFO_44

second_FIFO_block_44:
	movi	r1, 1
	movb	LBFIFO_flag,r1
	movi	r10, PCM_FIFO_1_START_44
write_to_FIFO_44:
#ifdef	EXECTIVE
#ifdef  QT_SYNC
	tsti	r4,0
	bne	Lskip_PTS_44

#if 0   // 5-7-98

	movh	r28,LIfrmsize
#if ISO
#ifndef MPEG_2
	shl	r28,1
#endif // MPEG_2
#else // ISO
#ifdef MPEG_2
        movb    r0,LBhdr_sampling_frequency
        tsti    r0,1
        beq     Lno_frmsize_shift
#endif // MPEG_2
	shl	r28,1
Lno_frmsize_shift:
#endif // ISO
	movw	r1,LWbytecount
	add	r1,r28
#if ISO
#ifdef MPEG_2
        movb    r0,LBhdr_padding
        tsti    r0,0
        beq     1f
        addi    r1,1
1:
#else // MPEG_2
        dlw     r0,frmsize_offset_cnt
	nop
        tsti    r0,0
        beq     Lno_offset
        subi    r0,1
        addi    r1,2
        dsw     r0,frmsize_offset_cnt
Lno_offset:	
#endif // MPEG_2
#else // ISO
#ifdef MPEG_2
        movb    r0,LBhdr_sampling_frequency
        tsti    r0,1
        bne     no_offset_vcd
        movb    r0,LBhdr_padding
        tsti    r0,0
        beq     1f
        addi    r1,1
1:
        j       Lno_offset
no_offset_vcd:
#endif // MPEG_2
        dlw     r0,frmsize_offset_cnt
	nop
        tsti    r0,0
        beq     Lno_offset
        subi    r0,1
        addi    r1,2
        dsw     r0,frmsize_offset_cnt
Lno_offset:	
#endif // ISO
	movw	LWbytecount,r1

#endif  // 0

	jsr	r28,SUB_check_PTS
Lskip_PTS_44:
#endif // QT_SYNC
#endif // EXECTIVE

        movi    r0, 0           //reset block count
        movb    LBout_blk, r0

	movw	r4,LWpcmscale	
	movi	DMASize, 31		;32 words each block
	movi	BlockSkip, 0	
	movi	BlockSize, 0		;block size = 1.

        // apply the gain to the samples
	movi	r0, 0xffff		//lower 16-bit mask
	mupi	r1, 0xffff		//upper 16-bit mask
	movi	AGRAdr0, local_pcm_sample_byte
        dlw     r3,KARAOKE_0
#ifdef	I2S
	movi	AGRAdr1, local_scaled_pcm_byte
        CLR_TrapReg_1
//      nop
//      nop
        andi    r3,0x3
        tsti    r3,3                    // check KARAOKE_0
        beq     Lswap_lr_44                // R=melody, L=vocal
        tsti    r3,2
        beq     Ll_to_lr_44                // R=vocal, L=vocal
        tsti    r3,1
        beq     Lr_to_lr_44                // R=melody, L=melody
                                        // default: R=vocal, L=melody
	loop	96, Lpcm_gain_loop_44
	shl	r3, a0(0*4), 16		//get lower 16-bit
	shra	r3, 8			//sign-extented to 1.23 format
	mulf	r6, r4, r3
	and	r3, r1, a0(1*4)		//get upper 16-bit; pipeline
	rnd	r6			
	shra	r3, 8			//sign-extented to 1.23 format
	mulf	r8, r4, r3
	nop		
	rnd	r8
	shl	a1(1*4), r6, 7		//L sample. align to MSB with 1 shift
	nop
	nop	
	shl	a1(1*4), r8, 7		//R sample. align to MSB with 1 shift
Lpcm_gain_loop_44:	
        j       Lend_of_gain_loop_44
Lswap_lr_44:
        loop    96, Lpcm_gain_loop_3_44
        and     r3, r1, a0(0*4)         //get upper 16-bit; pipeline
	shra	r3, 8			//sign-extented to 1.23 format
	mulf	r6, r4, r3
        shl     r3, a0(1*4), 16         //get lower 16-bit
	rnd	r6			
	shra	r3, 8			//sign-extented to 1.23 format
	mulf	r8, r4, r3
	nop		
	rnd	r8
	shl	a1(1*4), r6, 7		//L sample. align to MSB with 1 shift
	nop
	nop	
	shl	a1(1*4), r8, 7		//R sample. align to MSB with 1 shift
Lpcm_gain_loop_3_44:
        j       Lend_of_gain_loop_44
Lr_to_lr_44:
        loop    96, Lpcm_gain_loop_2_44
        and     r3, r1, a0(0*4)         //get upper 16-bit; pipeline
	shra	r3, 8			//sign-extented to 1.23 format
	mulf	r6, r4, r3
        nop
	rnd	r6			
	nop		
	nop		
	nop		
	shl	a1(1*4), r6, 7		//L sample. align to MSB with 1 shift
        shl     a1(1*4), r6, 7          //R sample. align to MSB with 1 shift
Lpcm_gain_loop_2_44:
        j       Lend_of_gain_loop_44
Ll_to_lr_44:
        loop    96, Lpcm_gain_loop_1_44
	shl	r3, a0(0*4), 16		//get lower 16-bit
	shra	r3, 8			//sign-extented to 1.23 format
	mulf	r6, r4, r3
        nop
	rnd	r6			
	nop		
	nop		
	nop		
	shl	a1(1*4), r6, 7		//L sample. align to MSB with 1 shift
        shl     a1(1*4), r6, 7          //R sample. align to MSB with 1 shift
Lpcm_gain_loop_1_44:
#else
        CLR_TrapReg_1
//      nop
//      nop
        andi    r3,0x3
        tsti    r3,3                    // check KARAOKE_0
        beq     Lswap_lr_44                // R=melody, L=vocal
        tsti    r3,2
        beq     Ll_to_lr_44                // R=vocal, L=vocal
        tsti    r3,1
        beq     Lr_to_lr_44                // R=melody, L=melody
                                        // default: R=vocal, L=melody
	loop	96, Lpcm_gain_loop_44
	and	r3, r1, a0(0*4)		//get upper 16-bit
	shra	r3, 8			//sign-extented to 1.23 format
	mulf	r6, r4, r3
	and	r3, r0, a0(0*4)		//get lower 16-bit; pipeline
	rnd	r6
	shl	r3, 16
	shra	r3, 8			//sign-extented to 1.23 format
	mulf	r8, r4, r3
	shl	r6, 8			//align to upper 16-bit; pipeline
	rnd	r8
	and	r6, r1			//keep only 16-bit data
	nop
	nop				//pipeline
	shr	r8, 8			//align to lower 16-bit
	and	r8, r0			//keep only 16-bit data
	or	a0(1*4), r6, r8		//put back 32-bit pair
Lpcm_gain_loop_44:
        j       Lend_of_gain_loop_44
Lswap_lr_44:
        loop    96, Lpcm_gain_loop_3_44
        and     r3, r1, a0(0*4)         //get upper 16-bit
	shra	r3, 8			//sign-extented to 1.23 format
	mulf	r6, r4, r3
	and	r3, r0, a0(0*4)		//get lower 16-bit; pipeline
	rnd	r6
	shl	r3, 16
	shra	r3, 8			//sign-extented to 1.23 format
	mulf	r8, r4, r3
        shr     r6, 8                   //align to lower 16-bit; pipeline
	rnd	r8
        and     r6, r0                  //keep only 16-bit data
	nop
	nop				//pipeline
        shl     r8, 8                   //align to upper 16-bit
        and     r8, r1                  //keep only 16-bit data
	or	a0(1*4), r6, r8		//put back 32-bit pair
Lpcm_gain_loop_3_44:
        j       Lend_of_gain_loop_44
Lr_to_lr_44:
        loop    96, Lpcm_gain_loop_2_44
        and     r3, r1, a0(0*4)         //get upper 16-bit
	shra	r3, 8			//sign-extented to 1.23 format
	mulf	r6, r4, r3
        nop
	rnd	r6
        nop
        nop
        nop
        shl     r8, r6, 8               //align to upper 16-bit
        and     r8, r1                  //keep only 16-bit data
        shr     r6, 8                   //align to lower 16-bit; pipeline
        and     r6, r0                  //keep only 16-bit data
	or	a0(1*4), r6, r8		//put back 32-bit pair
Lpcm_gain_loop_2_44:
        j       Lend_of_gain_loop_44
Ll_to_lr_44:
        loop    96, Lpcm_gain_loop_1_44
	and	r3, r0, a0(0*4)		//get lower 16-bit; pipeline
	shl	r3, 16
	shra	r3, 8			//sign-extented to 1.23 format
	mulf	r6, r4, r3
        nop
	rnd	r6
        nop
        nop
        nop
        shl     r8, r6, 8               //align to upper 16-bit
        and     r8, r1                  //keep only 16-bit data
        shr     r6, 8                   //align to lower 16-bit; pipeline
        and     r6, r0                  //keep only 16-bit data
	or	a0(1*4), r6, r8		//put back 32-bit pair
Lpcm_gain_loop_1_44:
#endif
Lend_of_gain_loop_44:
        SET_TrapReg

        // DMA scaled sample to FIFO
#ifdef	I2S
	movi	r3, local_scaled_pcm_word	; word addr
#else
	movi	r3, local_pcm_sample_word	; word addr
#endif
	shr	r9, r10, 2		; to word addr

	
        CLR_TrapReg
#ifdef	I2S
	loop	6, write_pcm_buf_44	;total of 32*3*2 words
#else
	loop	3, write_pcm_buf_44	;total of 32*3 words
#endif
	mov	LocalAddr, r3	
	dmawr	r9			;r10=FPApcmbufptr[outchan]=pcmptr2(init)
wait_dma_21_44:
	mov	r2,StatusPort
	tsti	r2,DmaDoneBit
	bz	wait_dma_21_44		;wait for dma done

	addi	r3, 32			;32 words each block
	addi	r9, 32
	
write_pcm_buf_44:
        SET_TrapReg

	
	movi	r9, PCM_FIFO_1_START_44
	tsti	r10, PCM_FIFO_0_START_44
	beq	toggle_FIFO_ptr_44
	movi	r9, PCM_FIFO_0_START_44

toggle_FIFO_ptr_44:
	movh	LIFIFO_BLK_PTR, r9	;toggle block ptr 
	movi	r1, 1
	movb	LBPCM_flag, r1		;set the flag
pcm_not_out_44:
.endif // PCM_OUT
	j	r26