📄 pcm_out.s
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bcnt=5, scnt=8, gcnt=3
dumping rountine:
if(bcnt) {
dump 35 samples;
bcnt--;
}
else {
dump 34 samples;
if(scnt>1) { // 8-2 or 7-2
scnt--;
bcnt=5;
}
else if (scnt=1) { // 1
scnt--;
bcnt=4;
}
else {
bcnt=5;
if (gcnt>1) { // 3-2
gcnt--;
scnt=8;
}
else if (gcnt=1) { // 1
gcnt--;
scnt=9;
}
else { // init
gcnt=3;
scnt=8;
}
}
}
//------------------------------------------------------------------
#endif // 0
#ifndef I2S
dlw r4, PCM_load_ptr
#endif // I2S
dlw r9, PCM_store_ptr
movi AGRSiz0, 0xffff
#ifdef I2S
movi AGRAdr0, local_scaled_pcm_byte
#else // I2S
mov AGRAdr0, r4
#endif // I2S
tsti r9,PCM_FIFO_SIZE
blt store_ptr_ok_48
movi r9,0
store_ptr_ok_48:
#ifndef I2S
addi r4,32*4
#endif // I2S
dlw r0, PCM_bcnt
mov r3, a0(1*4)
#ifdef I2S
mov r2, a0(1*4)
#endif // I2S
CLR_TrapReg_1
tsti r0, 0
beq insert_2_samples
// Insert 3 samples per block
subi r0, 1
dsw r0, PCM_bcnt
dswr r3, r9 // 1st inserted
addi r9, 4
#ifdef I2S
dswr r2, r9 // 1st inserted
addi r9, 4
#endif // I2S
tsti r9, PCM_FIFO_SIZE
blt reload_sample_i00
movi r9, 0
reload_sample_i00:
loop 11, write_pcm_buf_48_00 // 11 samples
dswr r3, r9
addi r9, 4
#ifdef I2S
dswr r2, r9
addi r9, 4
#endif // I2S
tsti r9, PCM_FIFO_SIZE
blt reload_sample_00
movi r9, 0
reload_sample_00:
mov r3, a0(1*4)
mov r2, a0(1*4)
write_pcm_buf_48_00:
dswr r3, r9 // 2nd inserted
addi r9, 4
#ifdef I2S
dswr r2, r9 // 2nd inserted
addi r9, 4
#endif
tsti r9, PCM_FIFO_SIZE
blt reload_sample_i10
movi r9, 0
reload_sample_i10:
loop 11, write_pcm_buf_48_10 // 11 samples
dswr r3, r9
addi r9, 4
#ifdef I2S
dswr r2, r9
addi r9, 4
#endif
tsti r9, PCM_FIFO_SIZE
blt reload_sample_10
movi r9, 0
reload_sample_10:
mov r3, a0(1*4)
mov r2, a0(1*4)
write_pcm_buf_48_10:
dswr r3, r9 // 3rd inserted
addi r9, 4
#ifdef I2S
dswr r2, r9 // 3rd inserted
addi r9, 4
#endif
tsti r9, PCM_FIFO_SIZE
blt reload_sample_i20
movi r9, 0
reload_sample_i20:
loop 10, write_pcm_buf_48_20 // 10 samples
dswr r3, r9
addi r9, 4
#ifdef I2S
dswr r2, r9
addi r9, 4
#endif
tsti r9, PCM_FIFO_SIZE
blt reload_sample_20
movi r9, 0
reload_sample_20:
mov r3, a0(1*4)
mov r2, a0(1*4)
write_pcm_buf_48_20:
j end_of_insertion
// Insert 2 samples per block
insert_2_samples:
dswr r3, r9 // 1st inserted
addi r9, 4
#ifdef I2S
dswr r2, r9 // 1st inserted
addi r9, 4
#endif
tsti r9, PCM_FIFO_SIZE
blt reload_sample_i100
movi r9, 0
reload_sample_i100:
loop 16, write_pcm_buf_48_100 // 16 samples
dswr r3, r9
addi r9, 4
#ifdef I2S
dswr r2, r9
addi r9, 4
#endif
tsti r9, PCM_FIFO_SIZE
blt reload_sample_100
movi r9, 0
reload_sample_100:
mov r3, a0(1*4)
mov r2, a0(1*4)
write_pcm_buf_48_100:
dswr r3, r9 // 2nd inserted
addi r9, 4
#ifdef I2S
dswr r2, r9 // 2nd inserted
addi r9, 4
#endif
tsti r9, PCM_FIFO_SIZE
blt reload_sample_i110
movi r9, 0
reload_sample_i110:
loop 16, write_pcm_buf_48_110 // 16 samples
dswr r3, r9
addi r9, 4
#ifdef I2S
dswr r2, r9
addi r9, 4
#endif
tsti r9, PCM_FIFO_SIZE
blt reload_sample_110
movi r9, 0
reload_sample_110:
mov r3, a0(1*4)
mov r2, a0(1*4)
write_pcm_buf_48_110:
dlw r0, PCM_scnt
movi r1, 5
tsti r0, 1
blte ChkScntEqOne
subi r0, 1
dsw r1, PCM_bcnt
dsw r0, PCM_scnt
j end_of_insertion
ChkScntEqOne:
bne ChkGroupCnt
subi r0, 1
movi r1, 4
dsw r0, PCM_scnt
dsw r1, PCM_bcnt
j end_of_insertion
ChkGroupCnt:
dlw r1, PCM_gcnt
movi r0, 5
dsw r0, PCM_bcnt
tsti r1, 1
blte ChkGcntEqOne
subi r1, 1
movi r0, 8
dsw r0, PCM_scnt
dsw r1, PCM_gcnt
j end_of_insertion
ChkGcntEqOne:
bne InitGcnt
subi r1, 1
movi r0, 9
dsw r0, PCM_scnt
dsw r1, PCM_gcnt
j end_of_insertion
InitGcnt:
movi r1, 3
movi r0, 8
dsw r0, PCM_scnt
dsw r1, PCM_gcnt
end_of_insertion:
SET_TrapReg
movi r1, 0
movb LBPCM_flag, r1 ;clr the flag
dlw r1, PCM_blk_cnt
nop
addi r1, 1
tsti r1, 3
blt store_blk_cnt
movi r1, 1
movb LBPCM_flag, r1 ;set the flag
#ifndef I2S
movi r4, local_pcm_sample_byte
#endif
movi r1, 0
store_blk_cnt:
#ifdef I2S
movi r4, local_scaled_pcm_byte
#endif
dsw r9, PCM_store_ptr
dsw r4, PCM_load_ptr
dsw r1, PCM_blk_cnt
pcm_not_out_48:
j r26
#endif // SR48
//---------------------------------------------
#if SPDIF_OUT
Out_fifo_spdif:
movb r0, LBhdr_lay
tsti r0, 1
bgt output_3_blocks //if layer_II, output now
movb r0, LBout_blk //if layer_I, accumulate 3 blocks
tsti r0, 3
beq Layer_I_out
movi r1, 1
movb LBPCM_flag, r1 ;set the flag so that main loop
//can continue
j r26 //return without output
Layer_I_out:
output_3_blocks:
.if PCM_OUT
movb r1, LBFIFO_flag
movb r4, LBblknum
tsti r1, 0
beq no_checking_FIFO
movh r10, LIFIFO_BLK_PTR
movi r8, PCM_FIFO_0_START_SP ; beginning of FIFO_0
movi r9, PCM_FIFO_0_END_SP ; to the end of FIFO being read
tsti r10, PCM_FIFO_0_START_SP
beq toggle_ref_ptr
movi r8, PCM_FIFO_1_START_SP ; beginning of FIFO_1
movi r9, PCM_FIFO_1_END_SP ; end of FIFO_1
toggle_ref_ptr:
;; read location of read fifo
pcmout_wait:
#ifdef FILE_OUT
dlw r1,PCM_Rd_Ptr ; read current pointer assigned by host
nop
#else
rlwi r1, PCM_Rd_Ptr ; read current pointer register (28c)
#endif
#ifdef STREAM_SIM
shr r1, 16 ; make it just the current address portion
#else
andi r1,0xffff
#endif
tst r1, r8
blt write_to_FIFO
tst r1, r9 ;
blte pcm_not_out ; if begin <= ptr <= end, wait
j write_to_FIFO
// write to the FIFO
;====write 3*32 words to main memory.
;this is modified to write 16-bit format of 2 channels to
;0 - 0x300 of the DRAM which is the PCM output FIFO.
no_checking_FIFO:
movb r0, LBhdr_lay
tsti r0, 1
bgt layer_II_fifo //if layer_II, check block 0
tsti r4, 2 //if layer_I, check block 2
bne second_FIFO_block
j continue_fifo
layer_II_fifo:
tsti r4, 0
bne second_FIFO_block
continue_fifo:
;;; set the size of the PCM output FIFO for 2 blocks
movi r1, PCM_FIFO_SIZE_SP ; size of PCM output FIFO
#ifdef STREAM_SIM
; 28c is PCM FIFO end address in real chip
; and should contain full address,seg+offset
; will be set by host for the time being.
rswi r1, 0x28c ; write to register
#endif
movi r10, PCM_FIFO_0_START_SP
j write_to_FIFO
second_FIFO_block:
movi r1, 1
movb LBFIFO_flag,r1
movi r10, PCM_FIFO_1_START_SP
write_to_FIFO:
#ifdef EXECTIVE
#ifdef QT_SYNC
tsti r4,0
bne Lskip_PTS
#if 0 // 5-7-98
movh r28,LIfrmsize
#if ISO
#ifndef MPEG_2
shl r28,1
#endif // MPEG_2
#else // ISO
#ifdef MPEG_2
movb r0,LBhdr_sampling_frequency
tsti r0,1
beq Lno_frmsize_shift
#endif // MPEG_2
shl r28,1
Lno_frmsize_shift:
#endif // ISO
movw r1,LWbytecount
add r1,r28
#if ISO
#ifdef MPEG_2
movb r0,LBhdr_padding
tsti r0,0
beq 1f
addi r1,1
1:
#else // MPEG_2
dlw r0,frmsize_offset_cnt
nop
tsti r0,0
beq Lno_offset
subi r0,1
addi r1,2
dsw r0,frmsize_offset_cnt
Lno_offset:
#endif // MPEG_2
#else // ISO
#ifdef MPEG_2
movb r0,LBhdr_sampling_frequency
tsti r0,1
bne no_offset_vcd
movb r0,LBhdr_padding
tsti r0,0
beq 1f
addi r1,1
1:
j Lno_offset
no_offset_vcd:
#endif // MPEG_2
dlw r0,frmsize_offset_cnt
nop
tsti r0,0
beq Lno_offset
subi r0,1
addi r1,2
dsw r0,frmsize_offset_cnt
Lno_offset:
#endif // ISO
movw LWbytecount,r1
#endif // 0
jsr r28,SUB_check_PTS
Lskip_PTS:
#endif // QT_SYNC
#endif // EXECTIVE
movi r0, 0 //reset block count
movb LBout_blk, r0
movw r4,LWpcmscale
movi DMASize, 31 ;32 words each block
movi BlockSkip, 0
movi BlockSize, 0 ;block size = 1.
// apply the gain to the samples
movi r0, 0xffff //lower 16-bit mask
mupi r1, 0xffff //upper 16-bit mask
movi AGRAdr0, local_pcm_sample_byte
CLR_TrapReg_1
dlw r3,KARAOKE_0
// nop
// nop
andi r3,0x3
tsti r3,3 // check KARAOKE_0
beq Lswap_lr_sp // R=melody, L=vocal
tsti r3,2
beq Ll_to_lr_sp // R=vocal, L=vocal
tsti r3,1
beq Lr_to_lr_sp // R=melody, L=melody
// default: R=vocal, L=melody
loop 96, Lpcm_gain_loop
and r3, r1, a0(0*4) //get upper 16-bit
shra r3, 8 //sign-extented to 1.23 format
mulf r6, r4, r3
and r3, r0, a0(0*4) //get lower 16-bit; pipeline
rnd r6
shl r3, 16
shra r3, 8 //sign-extented to 1.23 format
mulf r8, r4, r3
shl r6, 8 //align to upper 16-bit; pipeline
rnd r8
and r6, r1 //keep only 16-bit data
nop
nop //pipeline
shr r8, 8 //align to lower 16-bit
and r8, r0 //keep only 16-bit data
or a0(1*4), r6, r8 //put back 32-bit pair
Lpcm_gain_loop:
j Lend_of_gain_loop
Lswap_lr_sp:
loop 96, Lpcm_gain_loop_3
and r3, r1, a0(0*4) //get upper 16-bit
shra r3, 8 //sign-extented to 1.23 format
mulf r6, r4, r3
and r3, r0, a0(0*4) //get lower 16-bit; pipeline
rnd r6
shl r3, 16
shra r3, 8 //sign-extented to 1.23 format
mulf r8, r4, r3
shr r6, 8 //align to lower 16-bit; pipeline
rnd r8
and r6, r0 //keep only 16-bit data
nop
nop //pipeline
shl r8, 8 //align to upper 16-bit
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