📄 user.h
字号:
; Module: user
;
#include "dolby_pl.h"
#include "sync.h"
#ifdef EFFECT
#if THREEPAGE
#define PCM_IBUF_SIZE 0xf000 // 60k bytes
#define PCM_IBUF_START 0 // 0x5000
#else // THREEPAGE
#define PCM_IBUF_SIZE 0x6000 //0x5000 // 20k bytes
#define PCM_IBUF_START 0x5000
#endif // THREEPAGE
#define PCM_IBUF_END_plus1 PCM_IBUF_START+PCM_IBUF_SIZE
//efine PCM_MIN_IBUF_DEPTH 0x1000 //initial
#define PCM_MIN_IBUF_DEPTH 0x1800 //initial
#else //EFFECT
#define PCM_IBUF_SIZE 0xa000 // 40k bytes
#define PCM_IBUF_START 0x5000
#define PCM_IBUF_END_plus1 PCM_IBUF_START+PCM_IBUF_SIZE
#define PCM_MIN_IBUF_DEPTH 0x4000 //initial
#endif //EFFECT
#define IBUF_START PCM_IBUF_START
#define IBUF_END PCM_IBUF_START+PCM_IBUF_SIZE
#define IBUF_SIZE PCM_IBUF_SIZE
#define OBUF_SIZE 0x3000 // 12K bytes
#define OBUF_START 0x0000 // 1.5K words, 6K bytes
#define PROGRAM_START 0x1800 // 6K words, 24K bytes
// copy protection stuff
#define Drv_RD 0xfef0 // 5 byte
#define Drv_acc 0xfef8 // 1 byte 0xfef5
#define Drv_CD 0xfefc // 10 byte 0xfef6
//#define BUS_KEY0 0xff68
//#define BUS_KEY4 0xff6c
#define BUS_KEY0 0xf168
#define BUS_KEY4 0xf16c
#define PTS_FIFO_START 0xfa00 // 2 elements(PTS,byte count) per entry
#define PTS_FIFO_END 0xfe00
#define PTS_FIFO_SIZE (PTS_FIFO_END-PTS_FIFO_START)
#define PTS_FIFO_ENTRY (PTS_FIFO_END-PTS_FIFO_START)>>3
#define USER_DATA 0xff74
#define VER_SCALE 0xff78
#define USER_ICFG 0xff7c
#define USER_OCFG 0xff80
#define mic1_vol 0xff94
#define mic2_vol 0xff98
//************************************
//Vars added by ZhangWei
//#define mute_num 0xff9c
#define mute_num_mic 0xff9e
//************************************
// DiskAttrib: Low half for Disk Attribution, Hi half for seek snyc counter
// Low half: 0 = not seek yet, 1 = DTS CD, 2 = PCM CD
// Hi half: number of seeking sync
#define DiskAttrib 0xff90
#define INT_MASK 0xffa4
#define INT_STATUS 0xffa8
#define IN_BUFFER_THRESHOLD 0xffac //not used
#define PCM_SCALE 0xffb0
#define MUTE_BLK_CNT 0xffb4
#define PTS_FIFO_Start 0xffd0
#define PTS_FIFO_End 0xffd4
#define PTS_FIFO_Wr_Ptr 0xffd8
#define PTS_FIFO_Rd_Ptr 0xffdc
#ifdef STREAM_SIM
#define MEM_SEG 0
#define Stream_Enable 0x104
#define Stream_Start 0x108
#define Stream_Size 0x10c
#define Stream_Rd_Ptr 0x110
#define PCM_Out_Ctrl 0x284
#else
#if LS388
#if SVCD
#define MEM_SEG 0x9 //0x20
#if THREEPAGE
#define MEM_SEG12 0xb //0x22
#endif // THREEPAGE
#else // SVCD
#define MEM_SEG 0x10
#if THREEPAGE
#define MEM_SEG12 0x12
#endif // THREEPAGE
#endif // SVCD
#if 1
#define Comm_Reg0 0x100>>2
#define Comm_Reg1 0x104>>2
#define Comm_Reg2 0x108>>2
#define Comm_Reg3 0x918>>2 //0x10c>>2
#else // 1
#define Comm_Reg0 0x10>>2
#define Comm_Reg1 0x14>>2
#define Comm_Reg2 0x18>>2
#define Comm_Reg3 0x1c>>2
#endif // 1
#else // LS388
#define MEM_SEG 0x1f
#endif // LS388
#define Stream_Start 0xffe0
#define Stream_End 0xffe4
#define Stream_Wr_Ptr 0xffe8
#define Stream_Rd_Ptr 0xffec
#if LS388
#define Chip_Id (0x04>>2)
//#define Audio_CtrlReg (0x700>>2)
#define PCM_Run_Halt (0xe00>>2)
#define PCM_Out_Ctrl (0xe04>>2)
#define PCM_Start_Addr (0xe08>>2)
#define PCM_End_Addr (0xe0c>>2)
#define SPDIF_channel_status (0xe18>>2)
#define GPIO_CTRL_REG (0x44>>2)
#define PCM_In_Control_Reg (0xe20>>2)
#define PCM_In_Fifo_Start_Addr (0xe24>>2)
#define PCM_In_Fifo_End_Addr (0xe28>>2)
#define PCM_In_Current_Addr (0xe38>>2)
#define PLL_Ctrl_Reg1 (0xf0>>2)
#define PLL_Ctrl_Reg2 (0xf4>>2)
#define PLL_Off_Reg (0xf8>>2)
#define PLL_Clk_Div_Reg (0xfc>>2)
#define GenIOMIS_Read_Reg (0x1040>>2)
#define GenIOMIS_Tri_State_Enable (0x1048>>2)
#define GenIOMIS_Mode (0x1064>>2)
#else //LS388
#define PCM_Run_Halt (0x280>>2)
#define PCM_Out_Ctrl (0x284>>2)
#define PCM_Start_Addr (0x288>>2)
#define PCM_End_Addr (0x28c>>2)
#define SPDIF_channel_status (0x298>>2)
#define GPIO_CTRL_REG (0x350>>2)
#endif //LS388
#endif
#ifdef STREAM_SIM
#define PCM_Rd_Ptr 0x294
#else
#ifdef FILE_OUT
#define PCM_Rd_Ptr 0xffd8
#else
#if LS388
#define PCM_Rd_Ptr (0xe14>>2)
#else //LS388
#define PCM_Rd_Ptr (0x294>>2)
#endif //LS388
#endif
#endif
#define COMMAND0 0xfff0
#define COMMAND1 0xfff4
#define STATUS0 0xfff8
#define STATUS1 0xfffc
// executive host command
#define CMD_NOP 0x0
#define CMD_AC3 0x80
#define CMD_MPEG1 0x81
#define CMD_MPEG2 0x82
#define CMD_PCM 0x83
#define CMD_PLAY 0x84
#define CMD_STOPF 0x85
#define CMD_STOP 0x86
#define CMD_STOPB 0x87
#define CMD_UNMUTE 0x88
#define CMD_CONFIG 0x89
#define CMD_VER 0x8a
#define CMD_STAT 0x8b
#define CMD_GAIN 0X8c
#define SPDIF_ENABLED 0x1
#define CMD_FRAMES 0xa0
#define CMD_CPYP_CLEAR 0xa1
#define CMD_CPYP_DEC_AUTH 0xa2
#define CMD_CPYP_DRV_AUTH 0xa3
#define CMD_CPYP_KEY_SHARE 0xa4
#define CMD_CPYP_DISC_KEY 0xa5
#define CMD_CPYP_TITLE_KEY 0xa6
#define CMD_CPYP_SET_TK 0xa7
#define CMD_CPYP_DRIVER_TYPE 0xa8
#define CMD_SLOW_PLAY 0xb1
#define CMD_FAST_PLAY 0xb2
#define CMD_FF_FB_PLAY 0xb3
#define CMD_STEP_PLAY 0xb4
#define CMD_PAUSE_RESUME 0xb5
#define CMD_FORCE_DISPLAY 0xb6
#define CMD_NORMAL_PLAY 0xb7
#define CMD_SKIP_TO_I_FRAME 0xb8
#define CMD_FIELD_LOCK_ON 0xb9
#define CMD_FIELD_LOCK_OFF 0xba
#define CMD_NEW_AV_DELTA 0xbb
#define CMD1_QSOUND 0x800
#define CMD1_QSOUND_A 0x802 // QSurround with attenuation
#define CMD1_QSOUND_OFF 0x801
#define CMD1_AVF 0xa00
#define CMD1_AVF_OFF 0xa10
#define CMD1_AVF_L_ON 0xa01
#define CMD1_AVF_L_OFF 0xa11
#define CMD1_AVF_R_ON 0xa02
#define CMD1_AVF_R_OFF 0xa12
#define CMD1_AVF_LR_ON 0xa03
#define CMD1_AVF_LR_OFF 0xa13
#define CMD1_CS_ON 0xb00
#define CMD1_CS_OFF 0xb01
#define CS_DISABLED 0x0
#define CS_ENABLED 0x10
#define CS_PROCESSED 0x11
#define ERROR_MASK 0xf // bit 3..0
#define RUN_STOP_MASK 0x10 // bit 4
#define MUTE_MASK 0x20 // bit 5
#define PROCESSOR_MASK 0x700 // bit 10..8
#define FIRST_PCM_OUT 0x800 // bit 11
#define PAUSE 0x1000 // bit 12
#define NEW_OLD_MASK 0x4000 // bit 14
#define SYSINIT_MASK 0x8000 // bit 15
#define ICFG_CLOCK_MASK 0x0007
#define ICFG_CHAN_POLAR_MASK 0x0008
#define ICFG_PCM_SIZE_MASK 0x0030
#define ICFG_I2S_MASK 0x0040
#define ICFG_SPDIF_MASK 0x0080
#define ICFG_CLOCK_SHIFT 0
#define ICFG_CHAN_POLAR_SHIFT 3
#define ICFG_PCM_SIZE_SHIFT 4
#define ICFG_I2S_SHIFT 6
#define ICFG_SPDIF_SHIFT 7
//------New flag about KarlaOK system--------------------
#define ICFG_HWECHO_MASK 0x1000 //1 = HW-ECHO, 0 = SW-ECHO
#define ICFG_REVERB_BYPASS_MASK 0x2000 //1 = bypass reverb, 0 = reverb
#define ICFG_LS128_MASK 0x4000 //1 = LS128, 0 = not LS128
//-------------------------------------------------------
#define OCFG_MUTE_MASK 0x0040
#define OCFG_EMPHA_MASK 0x0080
#define OCFG_CHANNEL_MASK 0x0700
#define OCFG_PCM_FREQ_MASK 0x2000
#define OCFG_SAMP_FREQ_MASK 0x1000 // 0x3000
#define OCFG_WORD_LEN_MASK 0xc000
#define OCFG_Y_MASK_HI 0x001f
#define OCFG_X_MASK_HI 0x00e0
#define OCFG_MUTE_SHIFT 6
#define OCFG_EMPHA_SHIFT 7
#define OCFG_CHANNEL_SHIFT 8
#define OCFG_SAMP_FREQ_SHIFT 12
#define OCFG_WORD_LEN_SHIFT 14
#define OCFG_Y_SHIFT 16
#define OCFG_X_SHIFT 21
#define ROM_VER 0x100
#define STATUS_STOP 0x0
#define PROCESS_OLD 0x0
#define RESET_ERROR 0xfff0
#define RESET_ERR_SYNC 0xfffe
#define RESET_STOP 0xffef
#define SET_RUN 0x10
#define SET_MUTE 0x20
#define RESET_UNMUTE 0xffdf
#define SET_SYSINIT 0x8000 // set bit 15 to 1
#define RESET_SYSINIT 0x7fff
#define SET_PROCESS_NEW 0x4000 // set bit 14 to 1
#define RESET_PROCESS_OLD 0xbfff // set bit 14 to 0
#define SET_PAUSE 0x1000
#define RESET_RESUME 0xefff
#define PCM_DONE 0x1
#define SET_INT 0x4000 // Kluge way to set int
#define RESET_INT 0xbfff
/* host to fill 0xffffa5a5 in the stream buffer if end of stream reached
#define STREAM_END0 0xffff
#define STREAM_END1 0xa5a5
#define MAX_DMA_SIZE 32
*/
#if LS388
#define PLL_CTRL_48K 0x44E11000
#define PLL_DIV_48K 0x112
#define PLL_CTRL_441K 0x45431000
#define PLL_DIV_441K 0x08E
#define LS500_ID 0x00000000
#define LS508_ID 0x00000200
#define PLL_CTRL_48K_500 0x48AB1000
#define PLL_DIV_48K_500 0x46
#define PLL_CTRL_441K_500 0x0D0B1000
#define PLL_DIV_441K_500 0x15A
#define PLL_CTRL_48K_508 0x000108ab
#define PLL_DIV_48K_508 0x01110000
#define PLL_CTRL_441K_508 0x00000d0b
#define PLL_DIV_441K_508 0x01560000
#define CHANNEL_STATUS_48K 0x02000040
#define CHANNEL_STATUS_441K 0x02000000
#endif // LS388
// location of PCM_FIFO in main memory
#ifdef I2S // buffer size = 128 samples, 6 channels, 4 bytes per sample
#define PCM_FIFO_BASE 0
#define PCM_FIFO_0_START PCM_FIFO_BASE
#define PCM_FIFO_0_END PCM_FIFO_0_START+127*6*4
#define PCM_FIFO_1_START PCM_FIFO_BASE+256*3*4
#define PCM_FIFO_1_END PCM_FIFO_1_START+127*6*4
#define PCM_FIFO_SIZE 0x17ff
#else
#define PCM_FIFO_BASE 0
#define PCM_FIFO_0_START PCM_FIFO_BASE
#define PCM_FIFO_0_END PCM_FIFO_0_START+255*6*4
#define PCM_FIFO_1_START PCM_FIFO_BASE+256*6*4
#define PCM_FIFO_1_END PCM_FIFO_1_START+255*6*4
#define PCM_FIFO_SIZE 0x2fff
#endif
#define SP_draft_before_dram_byte 0x1800
#define SP_draft_before_dram_word 0x600
#define SP6_draft_before_dram_byte 0x1f00
#define SP6_draft_before_dram_word 0x800
#define RegStrWrPtr 0x914>>2
#define RegStrRdPtr 0x918>>2
#define RegPTSWrPtr 0x91c>>2
#define RegPTSRdPtr 0x920>>2
#if 1 /* Use DRAM for Pointers */
.MACRO LdStrRdPtr RegRdPtr
dlw \RegRdPtr,Stream_Rd_Ptr
.ENDM
.MACRO LdStrWrPtr RegWrPtr
dlw \RegWrPtr,Stream_Wr_Ptr
.ENDM
.MACRO SvStrRdPtr RegRdPtr
dsw \RegRdPtr,Stream_Rd_Ptr
.ENDM
.MACRO SvStrWrPtr RegWrPtr
dsw \RegWrPtr,Stream_Wr_Ptr
.ENDM
.MACRO LdPTSRdPtr RegRdPtr
dlw \RegRdPtr,PTS_FIFO_Rd_Ptr
.ENDM
.MACRO LdPTSWrPtr RegWrPtr
dlw \RegWrPtr,PTS_FIFO_Wr_Ptr
.ENDM
.MACRO SvPTSRdPtr RegRdPtr
dsw \RegRdPtr,PTS_FIFO_Rd_Ptr
.ENDM
.MACRO SvPTSWrPtr RegWrPtr
dsw \RegWrPtr,PTS_FIFO_Wr_Ptr
.ENDM
#else /* Use Register for Pointers */
.MACRO LdStrRdPtr RegRdPtr
rlwi \RegRdPtr,RegStrRdPtr
.ENDM
.MACRO LdStrWrPtr RegWrPtr
rlwi \RegWrPtr,RegStrWrPtr
.ENDM
.MACRO SvStrRdPtr RegRdPtr
rswi \RegRdPtr,RegStrRdPtr
.ENDM
.MACRO SvStrWrPtr RegWrPtr
rswi \RegWrPtr,RegStrWrPtr
.ENDM
.MACRO LdPTSRdPtr RegRdPtr
rlwi \RegRdPtr,RegPTSRdPtr
.ENDM
.MACRO LdPTSWrPtr RegWrPtr
rlwi \RegWrPtr,RegPTSWrPtr
.ENDM
.MACRO SvPTSRdPtr RegRdPtr
rswi \RegRdPtr,RegPTSRdPtr
.ENDM
.MACRO SvPTSWrPtr RegWrPtr
rswi \RegWrPtr,RegPTSWrPtr
.ENDM
#endif⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -