qq1.rpt

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 (41)    17    B       DFFE   +  t        0      0   0    4    5    3    2  |74160:32|QD (|74160:32|:9)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                               f:\shuzisuo\qq1.rpt
qq1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                         Logic cells placed in LAB 'B'
        +--------------- LC22 GL
        | +------------- LC23 JB
        | | +----------- LC24 RL
        | | | +--------- LC21 :44
        | | | | +------- LC20 |74160:32|QA
        | | | | | +----- LC19 |74160:32|QB
        | | | | | | +--- LC18 |74160:32|QC
        | | | | | | | +- LC17 |74160:32|QD
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC21 -> - - - - * * * * | - * | <-- :44
LC20 -> * * * * * * * * | - * | <-- |74160:32|QA
LC19 -> * * * - - * * * | - * | <-- |74160:32|QB
LC18 -> * * * - - - * * | - * | <-- |74160:32|QC
LC17 -> * * * - - * - * | - * | <-- |74160:32|QD

Pin
43   -> - - - - - - - - | - - | <-- CLK
11   -> * - * - * * * * | - * | <-- R0
9    -> * - * - * * * * | - * | <-- R1
8    -> * - * - * * * * | - * | <-- R2
7    -> * - * - * * * * | - * | <-- R3
6    -> * - * * - - - - | - * | <-- S0
5    -> * - * * - - - - | - * | <-- S1
4    -> * - * * - - - - | - * | <-- S2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               f:\shuzisuo\qq1.rpt
qq1

** EQUATIONS **

CLK      : INPUT;
R0       : INPUT;
R1       : INPUT;
R2       : INPUT;
R3       : INPUT;
S0       : INPUT;
S1       : INPUT;
S2       : INPUT;

-- Node name is 'GL' 
-- Equation name is 'GL', location is LC022, type is output.
 GL      = LCELL( _EQ001 $  GND);
  _EQ001 = !R0 &  R1 &  R2 & !R3 &  S0 & !S1 &  S2
         #  _LC017 &  _LC018 &  _LC019 &  S0 & !S1 &  S2
         # !_LC020 &  S0 & !S1 &  S2;

-- Node name is 'JB' 
-- Equation name is 'JB', location is LC023, type is output.
 JB      = LCELL( _EQ002 $  _LC020);
  _EQ002 =  _LC017 &  _LC018 &  _LC019 &  _LC020;

-- Node name is 'RL' 
-- Equation name is 'RL', location is LC024, type is output.
 RL      = LCELL( _EQ003 $  VCC);
  _EQ003 = !R0 &  R1 &  R2 & !R3 &  S0 & !S1 &  S2
         #  _LC017 &  _LC018 &  _LC019 &  S0 & !S1 &  S2
         # !_LC020 &  S0 & !S1 &  S2;

-- Node name is '|74160:32|:6' = '|74160:32|QA' 
-- Equation name is '_LC020', type is buried 
_LC020   = TFFE( _LC021, GLOBAL( CLK), !_EQ004,  VCC,  VCC);
  _EQ004 = !R0 &  R1 &  R2 & !R3;

-- Node name is '|74160:32|:7' = '|74160:32|QB' 
-- Equation name is '_LC019', type is buried 
_LC019   = TFFE( _EQ005, GLOBAL( CLK), !_EQ006,  VCC,  VCC);
  _EQ005 = !_LC017 &  _LC020 &  _LC021;
  _EQ006 = !R0 &  R1 &  R2 & !R3;

-- Node name is '|74160:32|:8' = '|74160:32|QC' 
-- Equation name is '_LC018', type is buried 
_LC018   = TFFE( _EQ007, GLOBAL( CLK), !_EQ008,  VCC,  VCC);
  _EQ007 =  _LC019 &  _LC020 &  _LC021;
  _EQ008 = !R0 &  R1 &  R2 & !R3;

-- Node name is '|74160:32|:9' = '|74160:32|QD' 
-- Equation name is '_LC017', type is buried 
_LC017   = DFFE( _EQ009 $  GND, GLOBAL( CLK), !_EQ010,  VCC,  VCC);
  _EQ009 =  _LC018 &  _LC019 &  _LC020 &  _LC021
         #  _LC017 & !_LC021
         #  _LC017 & !_LC020;
  _EQ010 = !R0 &  R1 &  R2 & !R3;

-- Node name is ':44' 
-- Equation name is '_LC021', type is buried 
_LC021   = DFFE( _EQ011 $ !_LC020, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ011 = !_LC020 &  S0 & !S1 &  S2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        f:\shuzisuo\qq1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,307K