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基于数字电路的数字钟制作

Protel Design System Design Rule Check
PCB File : shuzzhong .PCB
Date     : 3-Dec-2012 
Time     : 23:02:40

Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (On the board ) )
   Violation         Net GND   is broken into 7 sub-nets. Routed To 89.83%
     Subnet : J1-1     D6-com   D5-com   D4-com   D3-com   D2-com   D1-com   Ud-8     Uc-8     Ub-8     
              Ue-8     W0-1     U0-6     U0-8     Ua-8     Uf-8     U2-8     U1-8     C2-2     C1-2     U0-3     
              U0-4     U0-5     U3-8     C4-1     S2-2     C3-1     S1-2     U4-8     U5-8     U2-6     U1-6     
              U3-6     U2-3     U2-4     U2-5     U1-3     U1-4     U1-5     U4-6     U3-3     U3-4     U3-5     
              U5-6     U4-3     U4-4     U4-5     U5-3     U5-4     U5-5     G2-7     G1-7     
     Subnet : D6-com   
     Subnet : D5-com   
     Subnet : D4-com   
     Subnet : D3-com   
     Subnet : D2-com   
     Subnet : D1-com   
Rule Violations :1

Processing Rule : Clearance Constraint (Gap=0.254mm) (On the board ),(On the board )
Rule Violations :0

Processing Rule : Width Constraint (Min=0.8mm) (Max=0.8mm) (Prefered=0.8mm) (On the board )
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (On the board )
Rule Violations :0

Processing Rule : Width Constraint (Min=1.5mm) (Max=2mm) (Prefered=1.8mm) (Is on net GND )
Rule Violations :0

Processing Rule : Width Constraint (Min=1mm) (Max=1.5mm) (Prefered=1.2mm) (Is on net VCC )
Rule Violations :0


Violations Detected : 1
Time Elapsed        : 00:00:01