📄 str71x_os_2.s
字号:
;/*****************************************************************************/
;/* STARTUP.S: Startup file for ST STR71x device series */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>> */
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools. */
;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
;/* This software may only be used under the terms of a valid, current, */
;/* end user licence from KEIL for a compatible version of KEIL software */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/
;/*
; * The STARTUP.S code is executed after CPU Reset. This file may be
; * translated with the following SET symbols. In uVision these SET
; * symbols are entered under Options - ASM - Define.
; *
; * REMAP: when set the startup code initializes the register BOOTCR
; * which overwrites the settings of the CPU configuration pins. The
; * startup and interrupt vectors are remapped from:
; * 0x40000000 default setting
; * 0x60000000 when EXTMEM_MODE is used
; * 0x20000000 when RAM_MODE is used
; *
; * EXTMEM_MODE: when set the device is configured for code execution
; * from external memory starting at address 0x60000000. The startup
; * vectors are located to 0x60000000.
; *
; * RAM_MODE: when set the device is configured for code execution
; * from on-chip RAM starting at address 0x20000000. The startup
; * vectors are located to 0x20000000.
; */
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
;// <h> Stack Configuration (Stack Sizes in Bytes)
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
;// </h>
UND_Stack_Size EQU 0x00000000
SVC_Stack_Size EQU 0x00000008
ABT_Stack_Size EQU 0x00000000
FIQ_Stack_Size EQU 0x00000000
IRQ_Stack_Size EQU 0x00000100
USR_Stack_Size EQU 0x00000400
Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size)
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
Stack_Top EQU Stack_Mem + Stack_Size
;// <h> Heap Configuration
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
Heap_Mem SPACE Heap_Size
; APB Bridge 1 & 2 definitions (Peripherals)
APB1_BASE EQU 0xC0000000 ; APB Bridge 1 Base Address
APB2_BASE EQU 0xE0000000 ; APB Bridge 2 Base Address
CKDIS_OFS EQU 0x10 ; Clock Disable Register Offset
SWRES_OFS EQU 0x14 ; Software Reset Register Offset
APB1_Mask EQU 0x27FB ; APB1 Peripherals Mask
APB2_Mask EQU 0x7FDD ; APB2 Peripherals Mask
;// <e> Reset all Device Peripherals
PERIPH_RESET EQU 0
;// </e>
; External Memory Interface (EMI) definitions
EMI_BASE EQU 0x6C000000 ; EMI Base Address
BCON0_OFS EQU 0x00 ; BCON0 Offset
BCON1_OFS EQU 0x04 ; BCON1 Offset
BCON2_OFS EQU 0x08 ; BCON2 Offset
BCON3_OFS EQU 0x0C ; BCON3 Offset
;// <e> External Memory Interface (EMI)
EMI_SETUP EQU 0
;// <h> Bank Configuration 0 (BCON0)
;// <o.15> BE: Bank Enable
;// <o.0..1> B_SIZE: Bus Size <0=> 8-bit <1=> 16-bit
;// <2=> Reserved <3=> Reserved
;// <o.2..5> C_LENGTH: Cycle Length <0-15>
;// <i> Number of Wait States
;// </h>
BCON0_Val EQU 0x0000801D
;// <h> Bank Configuration 1 (BCON1)
;// <o.15> BE: Bank Enable
;// <o.0..1> B_SIZE: Bus Size <0=> 8-bit <1=> 16-bit
;// <2=> Reserved <3=> Reserved
;// <o.2..5> C_LENGTH: Cycle Length <0-15>
;// <i> Number of Wait States
;// </h>
BCON1_Val EQU 0x0000801D
;// <h> Bank Configuration 2 (BCON2)
;// <o.15> BE: Bank Enable
;// <o.0..1> B_SIZE: Bus Size <0=> 8-bit <1=> 16-bit
;// <2=> Reserved <3=> Reserved
;// <o.2..5> C_LENGTH: Cycle Length <0-15>
;// <i> Number of Wait States
;// </h>
BCON2_Val EQU 0x0000001D
;// <h> Bank Configuration 3 (BCON3)
;// <o.15> BE: Bank Enable
;// <o.0..1> B_SIZE: Bus Size <0=> 8-bit <1=> 16-bit
;// <2=> Reserved <3=> Reserved
;// <o.2..5> C_LENGTH: Cycle Length <0-15>
;// <i> Number of Wait States
;// </h>
BCON3_Val EQU 0x0000001D
;// </e> End of EMI
; GPIO Port 2 definitions (for External Memory Interface setup)
GPIO2_BASE EQU 0xE0005000 ; GPIO2 Base Address
PC0_OFS EQU 0x00 ; PC0 Offset
PC1_OFS EQU 0x04 ; PC1 Offset
PC2_OFS EQU 0x08 ; PC2 Offset
PD_OFS EQU 0x0C ; PD Offset
; Enhanced Interrupt Controller (EIC) definitions
EIC_BASE EQU 0xFFFFF800 ; EIC Base Address
ICR_OFS EQU 0x00 ; Interrupt Control Reg. Offset
CIPR_OFS EQU 0x08 ; Curr. Int. Priority R. Offset
IVR_OFS EQU 0x18 ; Interrupt Vector Reg. Offset
FIR_OFS EQU 0x1C ; Fast Interrupt Reg. Offset
IER_OFS EQU 0x20 ; Interrupt Enable Reg. Offset
IPR_OFS EQU 0x40 ; Interrupt Pending Reg. Offset
SIR0_OFS EQU 0x60 ; Source Interrupt Reg. 0 Offset
;// <e> Setup EIC and Exception Handlers
EIC_SETUP EQU 1
;// </e>
PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.
EXPORT Vectors
AREA Reset, CODE, READONLY
ARM
IF EIC_SETUP <> 0
; Import Exceptions Handlers
IMPORT UndefHandler
IMPORT SWIHandler
IMPORT PAbtHandler
IMPORT DAbtHandler
IMPORT OS_CPU_IRQ_ISR
IMPORT OS_CPU_FIQ_ISR
; Import IRQ Handlers
IMPORT T0TIMI_IRQHandler
IMPORT FLASH_IRQHandler
IMPORT RCCU_IRQHandler
IMPORT RTC_IRQHandler
IMPORT WDG_IRQHandler
IMPORT XTI_IRQHandler
IMPORT USBHP_IRQHandler
IMPORT I2C0ITERR_IRQHandler
IMPORT I2C1ITERR_IRQHandler
IMPORT UART0_IRQHandler
IMPORT UART1_IRQHandler
IMPORT UART2_IRQHandler
IMPORT UART3_IRQHandler
IMPORT BSPI0_IRQHandler
IMPORT BSPI1_IRQHandler
IMPORT I2C0_IRQHandler
IMPORT I2C1_IRQHandler
IMPORT CAN_IRQHandler
IMPORT ADC12_IRQHandler
IMPORT T1TIMI_IRQHandler
IMPORT T2TIMI_IRQHandler
IMPORT T3TIMI_IRQHandler
IMPORT HDLC_IRQHandler
IMPORT USBLP_IRQHandler
IMPORT T0TOI_IRQHandler
IMPORT T0OC1_IRQHandler
IMPORT T0OC2_IRQHandler
ENDIF
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors
LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
NOP ; Reserved Vector
IF EIC_SETUP <> 0
LDR PC,IRQ_Addr
ELSE
LDR PC,[PC, #-0x0808] ; Vector from EIC_IVR
ENDIF
LDR PC, FIQ_Addr
Reset_Addr DCD Reset_Handler
Undef_Addr DCD UndefHandler
SWI_Addr DCD SWIHandler
PAbt_Addr DCD PAbtHandler
DAbt_Addr DCD DAbtHandler
DCD 0 ; Reserved Address
IRQ_Addr DCD IRQHandler
FIQ_Addr DCD FIQHandler
IF EIC_SETUP = 0
UndefHandler B UndefHandler
SWIHandler B SWIHandler
PAbtHandler B PAbtHandler
DAbtHandler B DAbtHandler
IRQHandler B IRQHandler
FIQHandler B FIQHandler
ELSE
; Peripherals IRQ Handlers Address Table
EXPORT T0TIMI_Addr
T0TIMI_Addr DCD T0TIMIIRQHandler
FLASH_Addr DCD FLASHIRQHandler
RCCU_Addr DCD RCCUIRQHandler
RTC_Addr DCD RTCIRQHandler
WDG_Addr DCD WDGIRQHandler
XTI_Addr DCD XTIIRQHandler
USBHP_Addr DCD USBHPIRQHandler
I2C0ITERR_Addr DCD I2C0ITERRIRQHandler
I2C1ITERR_Addr DCD I2C1ITERRIRQHandler
UART0_Addr DCD UART0IRQHandler
UART1_Addr DCD UART1IRQHandler
UART2_Addr DCD UART2IRQHandler
UART3_Addr DCD UART3IRQHandler
BSPI0_Addr DCD BSPI0IRQHandler
BSPI1_Addr DCD BSPI1IRQHandler
I2C0_Addr DCD I2C0IRQHandler
I2C1_Addr DCD I2C1IRQHandler
CAN_Addr DCD CANIRQHandler
ADC12_Addr DCD ADC12IRQHandler
T1TIMI_Addr DCD T1TIMIIRQHandler
T2TIMI_Addr DCD T2TIMIIRQHandler
T3TIMI_Addr DCD T3TIMIIRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
HDLC_Addr DCD HDLCIRQHandler
USBLP_Addr DCD USBLPIRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
T0TOI_Addr DCD T0TOIIRQHandler
T0OC1_Addr DCD T0OC1IRQHandler
T0OC2_Addr DCD T0OC2IRQHandler
ENDIF
; Reset Handler
EXPORT Reset_Handler
Reset_Handler
NOP ; Wait for OSC stabilization
NOP
NOP
NOP
NOP
NOP
NOP
NOP
; Reset Peripherals
IF PERIPH_RESET <> 0
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -