71x_init.s

ucos_ii在str710f2z6上的移植及串口驱动（包含了fifo）源代码。其中“读我。txt”文件中有移植时做的简单笔记。希望对需要的初学者有所帮助。

;******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
;* File Name          : 71x_init.s
;* Author             : MCD Application Team
;* Date First Issued  : 06/23/2004
;* Description        : This is the first code executed after RESET.
;*                      This code used to initialize system stacks
;*                      and critical peripherals before entering the C code.
;*******************************************************************************
;* History:
;*  13/01/2006 : V3.1
;*  24/05/2005 : V3.0
;*  30/11/2004 : V2.0
;*  14/07/2004 : V1.3
;*  01/01/2004 : V1.2
;*******************************************************************************
; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************/

        PRESERVE8
        AREA    Init, CODE, READONLY


; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

Mode_USR            EQU    0x10
Mode_FIQ            EQU    0x11
Mode_IRQ            EQU    0x12
Mode_SVC            EQU    0x13
Mode_ABT            EQU    0x17
Mode_UNDEF          EQU    0x1B
Mode_SYS            EQU    0x1F ; available on ARM Arch 4 and later

I_Bit               EQU    0x80 ; when I bit is set, IRQ is disabled
F_Bit               EQU    0x40 ; when F bit is set, FIQ is disabled


; --- System memory locations

RAM_Base            EQU    0x20000000
RAM_Limit           EQU    0x20010000
SRAM_Base           EQU    0x60000000
Stack_Base          EQU    RAM_Limit


USR_Stack_Length    EQU    4096
IRQ_Stack_Length    EQU    1024
SVC_Stack_Length    EQU    256
FIQ_Stack_Length    EQU    256
ABT_Stack_Length    EQU    256
UNDEF_Stack_Length  EQU    256


USR_Stack           EQU    Stack_Base                 ; USR stack
IRQ_Stack           EQU    USR_Stack-USR_Stack_Length ; followed by IRQ stack
SVC_Stack           EQU    IRQ_Stack-IRQ_Stack_Length ; followed by SVC stack
FIQ_Stack           EQU    SVC_Stack-SVC_Stack_Length ; followed by FIQ stack
ABT_Stack           EQU    FIQ_Stack-FIQ_Stack_Length ; followed by ABT stack
UNDEF_Stack         EQU    ABT_Stack-ABT_Stack_Length ; followed by UNDEF stack
;===================================================================================
Stack_Size	EQU	(USR_Stack_Length+IRQ_Stack_Length+SVC_Stack_Length+\
				 FIQ_Stack_Length+ABT_Stack_Length+UNDEF_Stack_Length	)

                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem		SPACE	 Stack_Size
Heap_Size       EQU     0x00000000
                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
Heap_Mem        SPACE   Heap_Size
;====================================================================================

EIC_Base_addr       EQU    0xFFFFF800; EIC base address
ICR_off_addr        EQU    0x00      ; Interrupt Control register offset
CIPR_off_addr       EQU    0x08      ; Current Interrupt Priority Register offset
IVR_off_addr        EQU    0x18      ; Interrupt Vector Register offset
FIR_off_addr        EQU    0x1C      ; Fast Interrupt Register offset
IER_off_addr        EQU    0x20      ; Interrupt Enable Register offset
IPR_off_addr        EQU    0x40      ; Interrupt Pending Bit Register offset
SIR0_off_addr       EQU    0x60      ; Source Interrupt Register 0

EMI_Base_addr       EQU    0x6C000000; EMI base address
BCON0_off_addr      EQU    0x00      ; Bank 0 configuration register offset
BCON1_off_addr      EQU    0x04      ; Bank 1 configuration register offset
BCON2_off_addr      EQU    0x08      ; Bank 2 configuration register offset
BCON3_off_addr      EQU    0x0C      ; Bank 3 configuration register offset

EMI_ENABLE          EQU    0x8000
EMI_SIZE_16         EQU    0x0001

GPIO2_Base_addr     EQU    0xE0005000; GPIO2 base address
PC0_off_addr        EQU    0x00      ; Port Configuration Register 0 offset
PC1_off_addr        EQU    0x04      ; Port Configuration Register 1 offset
PC2_off_addr        EQU    0x08      ; Port Configuration Register 2 offset
PD_off_addr         EQU    0x0C      ; Port Data Register offset

CPM_Base_addr       EQU    0xA0000040; CPM Base Address
BOOTCR_off_addr     EQU    0x10      ; CPM - Boot Configuration Register
FLASH_mask          EQU    0x0000    ; to remap FLASH at 0x0
RAM_mask            EQU    0x0002    ; to remap RAM at 0x0
EXTMEM_mask         EQU    0x0003    ; to remap EXTMEM at 0x0

;|----------------------------------------------------------------------------------|
;| - APB Bridge  (System Peripheral)                                               |
;|----------------------------------------------------------------------------------|
APB1_base_addr      EQU    0xC0000000          ; APB Bridge1 Base Address
APB2_base_addr      EQU    0xE0000000          ; APB Bridge2 Base Address
CKDIS_off_addr      EQU    0x10                ; APB Bridge1 - Clock Disable  Register
SWRES_off_addr      EQU    0x14                ; APB Bridge1 - Software Reset Register
CKDIS1_config_all   EQU    0x27FB              ; To enable/disable clock of all APB1's peripherals
SWRES1_config_all   EQU    0x27FB              ; To reset all APB1's peripherals
CKDIS2_config_all   EQU    0x7FDD              ; To enable/disable clock of all APB2's peripherals
SWRES2_config_all   EQU    0x7FDD              ; To reset all APB2's peripherals

;*******************************************************************************
;*******                         -- MACROS --                            *******
;*******************************************************************************
;*******************************************************************************
;* Macro Name     : EMI_INIT
;* Description    : This macro Initialize EMI bank 1: 16-bit 7 wait state
;* Input          : None.
;* Output         : None.
;*******************************************************************************
        MACRO   
        EMI_INIT
        LDR     r0, =GPIO2_Base_addr      ; Configure P2.0 -> 3 in AF_PP mode
        LDR     r2, [r0, #PC0_off_addr]
        ORR     r2, r2,#0x0000000F
        STR     r2, [r0, #PC0_off_addr]
        LDR     r2, [r0, #PC1_off_addr]
        ORR     r2, r2,#0x0000000F
        STR     r2, [r0, #PC1_off_addr]
        LDR     r2, [r0, #PC2_off_addr]
        ORR     r2, r2,#0x0000000F
        STR     r2, [r0, #PC2_off_addr]
        LDR     r0, =EMI_Base_addr
        LDR     r1, =0x18:OR:EMI_ENABLE:OR:EMI_SIZE_16
        STR     r1, [r0, #BCON1_off_addr] ; Enable bank 1 16-bit 7 wait state
        MEND
;*******************************************************************************
;* Macro Name     : EIC_INIT
;* Description    : This macro Initialize the EIC as following :
;                 - IRQ disabled
;                 - FIQ disabled
;                 - IVR contain the load PC opcode (0xE59FFXXX)
;                 - Current priority level equal to 0
;                 - All channels are disabled
;                 - All channels priority equal to 0
;                 - All SIR registers contain offset to the related IRQ
;                   table entry
;* Input          : None.
;* Output         : None.
;*******************************************************************************
        MACRO   
        EIC_INIT
        LDR     r3, =EIC_Base_addr
        MOV     r0, #0
        MVN     r1, #0
        MOV     r2, #0x0c
        STR     r0, [r3, #ICR_off_addr]
        STR     r0, [r3, #IER_off_addr]
        STR     r1, [r3, #IPR_off_addr]
        STR     r2, [r3, #FIR_off_addr]
        STR     r0, [r3, #CIPR_off_addr]
        
        LDR     r4, =0xE59F0000

        STR     r4, [r3, #IVR_off_addr]; Write the LDR pc,[pc,#offset]
                                       ; instruction code in IVR[31:16]
        LDR     r2, =32                ; 32 Channel to initialize
        LDR     r0, =T0TIMI_Addr       ; Read the address of the IRQs
                                       ; address table
        LDR     r1, =0x00000FFF
        AND     r0,r0,r1
        LDR     r5, =SIR0_off_addr     ; Read SIR0 address
        SUB     r4,r0,#8               ; Subtract 8 for prefetch
        LDR     r1, =0xF7E8            ; Add the offset from IVR to 0x00000000
                                       ; address(IVR address + 7E8 = 0x00000000)
                                       ; 0xF7E8 used to complete the