📄 str71x.s
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PrefetchAbortHandler_1
SUB lr,lr,#4 ;更新连接寄存器lr
SaveContext r0,r11 ;保存当前工作寄存器及
;lr_abt和spsr_abt到堆栈中
BL Prefetch_Handler ;跳转到C语言函数Prefetch_Handler.
RestoreContext r0,r11 ;返回到产生预取指中止异常的指令的下一条指令
DataAbortHandler_1
SUB lr,lr,#8 ;更新连接寄存器lr
SaveContext r0,r11 ;保存当前工作寄存器及
;lr_abt和spsr_abt到堆栈中
BL Abort_Handler ;跳转到C语言函数Abort_Handler.
RestoreContext r0,r11 ;返回到产生数据中止异常的指令的下一条指令
MACRO
IRQ_to_SYS ; （3）
MSR cpsr_c,#0x1F ;切换到系统模式
STMFD sp!,{lr} ;保存连接寄存器lr到堆栈中
MEND
MACRO
SYS_to_IRQ ; （4）
LDMFD sp!,{lr} ;恢复连接寄存器lr
MSR cpsr_c,#0xD2 ;切换到IRQ模式
; MOV pc,lr ;返回
BX LR;
MEND
T0TIMIIRQHandler_1
IRQ_to_SYS
BL T0TIMI_IRQHandler
SYS_to_IRQ
FLASHIRQHandler_1
IRQ_to_SYS
BL FLASH_IRQHandler
SYS_to_IRQ
RCCUIRQHandler_1
IRQ_to_SYS
BL RCCU_IRQHandler
SYS_to_IRQ
RTCIRQHandler_1
IRQ_to_SYS
BL RTC_IRQHandler
SYS_to_IRQ
WDGIRQHandler_1
IRQ_to_SYS
BL WDG_IRQHandler
SYS_to_IRQ
XTIIRQHandler_1
IRQ_to_SYS
BL XTI_IRQHandler
SYS_to_IRQ
USBHPIRQHandler_1
IRQ_to_SYS
BL USBHP_IRQHandler
SYS_to_IRQ
I2C0ITERRIRQHandler_1
IRQ_to_SYS
BL I2C0ITERR_IRQHandler
SYS_to_IRQ
I2C1ITERRIRQHandler_1
IRQ_to_SYS
BL I2C1ITERR_IRQHandler
SYS_to_IRQ
UART0IRQHandler_1
IRQ_to_SYS
BL UART0_IRQHandler
SYS_to_IRQ
UART1IRQHandler_1
IRQ_to_SYS
BL UART1_IRQHandler
SYS_to_IRQ
UART2IRQHandler_1
IRQ_to_SYS
BL UART2_IRQHandler
SYS_to_IRQ
UART3IRQHandler_1
IRQ_to_SYS
BL UART3_IRQHandler
SYS_to_IRQ
BSPI0IRQHandler_1
IRQ_to_SYS
BL BSPI0_IRQHandler
SYS_to_IRQ
BSPI1IRQHandler_1
IRQ_to_SYS
BL BSPI1_IRQHandler
SYS_to_IRQ
I2C0IRQHandler_1
IRQ_to_SYS
BL I2C0_IRQHandler
SYS_to_IRQ
I2C1IRQHandler_1
IRQ_to_SYS
BL I2C1_IRQHandler
SYS_to_IRQ
CANIRQHandler_1
IRQ_to_SYS
BL CAN_IRQHandler
SYS_to_IRQ
ADC12IRQHandler_1
IRQ_to_SYS
BL ADC12_IRQHandler
SYS_to_IRQ
T1TIMIIRQHandler_1
IRQ_to_SYS
BL T1TIMI_IRQHandler
SYS_to_IRQ
T2TIMIIRQHandler_1
IRQ_to_SYS
BL T2TIMI_IRQHandler
SYS_to_IRQ
T3TIMIIRQHandler_1
IRQ_to_SYS
BL T3TIMI_IRQHandler
SYS_to_IRQ
HDLCIRQHandler_1
IRQ_to_SYS
BL HDLC_IRQHandler
SYS_to_IRQ
USBLPIRQHandler_1
IRQ_to_SYS
BL USBLP_IRQHandler
SYS_to_IRQ
T0TOIIRQHandler_1
IRQ_to_SYS
BL T0TOI_IRQHandler
SYS_to_IRQ
T0OC1IRQHandler_1
IRQ_to_SYS
BL T0OC1_IRQHandler
SYS_to_IRQ
T0OC2IRQHandler_1
IRQ_to_SYS
BL T0OC2_IRQHandler
SYS_to_IRQ
;============================================================================
; Reset Handler
EXPORT Reset_Handler
Reset_Handler
NOP ; Wait for OSC stabilization
NOP
NOP
NOP
NOP
NOP
NOP
NOP
; Reset Peripherals
IF PERIPH_RESET <> 0
LDR R1, =APB1_BASE
LDR R2, =APB2_BASE
LDR R3, =APB1_Mask
LDR R4, =APB2_Mask
STRH R3, [R1, #CKDIS_OFS] ; Disable Clock for APB1 periph.
STRH R4, [R2, #CKDIS_OFS] ; Disable Clock for APB2 periph.
STRH R3, [R1, #SWRES_OFS] ; Keep under Reset APB1 periph.
STRH R4, [R2, #SWRES_OFS] ; Keep under Reset APB2 periph.
MOV R0, #10
PR_Loop1 SUBS R0, R0, #1 ; Wait that selected macrocells
BNE PR_Loop1 ; enter reset
STRH R0, [R1, #SWRES_OFS] ; Release Reset of APB1 periph.
STRH R0, [R2, #SWRES_OFS] ; Relase Reset of APB2 periph.
STRH R0, [R1, #CKDIS_OFS] ; Enable Clock for APB1 periph.
STRH R0, [R2, #CKDIS_OFS] ; Enable Clock for APB2 periph.
MOV R0, #10
PR_Loop2 SUBS R0, R0, #1 ; Wait that selected macrocells
BNE PR_Loop2 ; exit from reset
ENDIF
; Setup External Memory Interface (EMI)
IF EMI_SETUP <> 0
LDR R0, =GPIO2_BASE ; Configure P2.0..7 for Ext. Bus
LDR R1, [R0, #PC0_OFS]
ORR R1, R1, #0x0000000F
STR R1, [R0, #PC0_OFS]
LDR R1, [R0, #PC1_OFS]
ORR R1, R1, #0x0000000F
STR R1, [R0, #PC1_OFS]
LDR R1, [R0, #PC2_OFS]
ORR R1, R1, #0x0000000F
STR R1, [R0, #PC2_OFS]
LDR R0, =EMI_BASE ; Configure EMI
LDR R1, =BCON0_Val
STR R1, [R0, #BCON0_OFS]
LDR R1, =BCON1_Val
STR R1, [R0, #BCON1_OFS]
LDR R1, =BCON2_Val
STR R1, [R0, #BCON2_OFS]
LDR R1, =BCON3_Val
STR R1, [R0, #BCON3_OFS]
ENDIF
; Setup Enhanced Interrupt Controller
IF EIC_SETUP <> 0
LDR R0, =EIC_BASE
LDR R1, =0xE59F0000 ; LDR PC,[PC,#ofs] (High 16-bits)
STR R1, [R0, #IVR_OFS] ; Store into IVR[31:16]
LDR R1, =T0TIMI_Addr ; IRQ Address Table
LDR R2, =0x0FFF ; Offset Mask
AND R1, R1, R2 ; Mask Offset
LDR R2, =0xF7E0 ; Jump Offset = 0x07E0
; 0xFXXX is used to complete the
; LDR PC,[PC,#ofs]
; 0x07E0 = 0x07E8 - 8 (Prefetch)
; 0 = IVR Address + 0x7E8
ADD R1, R1, R2 ; Add Jump Offset
MOV R2, #32 ; Number of Channels
MOV R3, #SIR0_OFS ; Offset to SIR0
EIC_Loop MOV R4, R1, LSL #16 ; Use High 16-bits
STR R4, [R0, R3] ; Store into SIRx
ADD R1, R1, #4 ; Next IRQ Address
ADD R3, R3, #4 ; Next SIRx
SUBS R2, R2, #1 ; Decrement Counter
BNE EIC_Loop
ENDIF
; Memory Remapping
BOOTCR EQU 0xA0000050 ; Boot Configuration Register
FLASH_BM EQU 0x01 ; Boot Mode: Flash at 0
RAM_BM EQU 0x02 ; Boot Mode: RAM at 0
EXTMEM_BM EQU 0x03 ; Boot Mode: EXTMEM at 0
IF :DEF:REMAP
MOV R1, #FLASH_BM
IF :DEF:EXTMEM_MODE
MOV R1, #EXTMEM_BM
ENDIF
IF :DEF:RAM_MODE
MOV R1, #RAM_BM
ENDIF
LDR R0, =BOOTCR
LDRH R2, [R0] ; Read BOOTCR
BIC R2, R2, #0x03 ; Clear two LSB bits
ORR R2, R2, R1 ; Setup two LSB bits
STRH R2, [R0] ; Write BOOTCR
ENDIF
; Setup Stack for each mode
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
; Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
; Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SYS:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB SL, SP, #USR_Stack_Size
MSR CPSR_c, #Mode_SYS
; Enter the C code
IMPORT __main
LDR R0, =__main
BX R0
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + USR_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
END
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