cs8900.java

Java Op Processor java vhdl processor

package ejip;

/**
*	CS8900.java
*
*	Low level interface to Cirrus Logic ethernet chip CS8900A.
*
*	Adapted from cs89x0.c driver for linux by 
*		Martin Schoeberl ([e-mail])
*
*	Written 1996 by Russell Nelson, with reference to skeleton.c
*	written 1993-1994 by Donald Becker.
*	Copyright, 1988-1992, Russell Nelson, Crynwr Software
*
*	This program is free software; you can redistribute it and/or modify
*	it under the terms of the GNU General Public License as published by
*	the Free Software Foundation, version 1.
*
*	This program is distributed in the hope that it will be useful,
*	but WITHOUT ANY WARRANTY; without even the implied warranty of
*	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*	GNU General Public License for more details.
*
*	You should have received a copy of the GNU General Public License
*	along with this program; if not, write to the Free Software
*	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*		The author may be reached at [e-mail], Crynwr
*		Software, 521 Pleasant Valley Rd., Potsdam, NY 13676
*
*   Changelog:
*		2002-06-28	first working version
*		2002-10-xx	some optimations, use Packet buffer (in 32 bit)
*		2002-11-11	runs it its own thread (as LinkLayer)
*		2004-08-19	longer time for read/write (nior/w low) for 100 MHz JOP
*/

import util.Dbg;

import com.jopdesign.sys.Const;
import com.jopdesign.sys.Native;

/**
*	Low level interface to Cirrus Logic ethernet chip CS8900A.
*
*/

public class CS8900 extends LinkLayer {

	public static final int ETH_HLEN = 14;

/**
*	flag allows new frame to be sent.
*/
	private static boolean txFree;			// ready for next transmit

	static int[] eth;				// own ethernet address
	private static int mac_low, mac_mid, mac_hi;
	static int ip;					// ip address for the interface


	private static int tx_packets;
//	private static int tx_bytes;
//	private static int collisions;

	private static int rx_packets;
	private static int rx_bytes;
	private static int rx_dropped;

	private static int curr_rx_cfg;	/* a copy of PP_RxCFG */

/******** cs.h **********/

//	private static final int PP_ISAIOB = 0x0020;	/*  IO base address */

	private static final int PP_RxCFG = 0x0102;		/*  Rx Bus config */
	private static final int PP_RxCTL = 0x0104;		/*  Receive Control Register */
	private static final int PP_TxCFG = 0x0106;		/*  Transmit Config Register */
//	private static final int PP_TxCMD = 0x0108;		/*  Transmit Command Register */
	private static final int PP_BufCFG = 0x010A;	/*  Bus configuration Register */
	private static final int PP_LineCTL = 0x0112;	/*  Line Config Register */
//	private static final int PP_SelfCTL = 0x0114;	/*  Self Command Register */
	private static final int PP_BusCTL = 0x0116;	/*  ISA bus control Register */
//	private static final int PP_TestCTL = 0x0118;	/*  Test Register */
//	private static final int PP_AutoNegCTL = 0x011C;	/*  Auto Negotiation Ctrl */

//	private static final int PP_ISQ = 0x0120;		/*  Interrupt Status */
	private static final int PP_RxEvent = 0x0124;	/*  Rx Event Register */
	private static final int PP_TxEvent = 0x0128;	/*  Tx Event Register */
	private static final int PP_BufEvent = 0x012C;	/*  Bus Event Register */
//	private static final int PP_RxMiss = 0x0130;	/*  Receive Miss Count */
//	private static final int PP_TxCol = 0x0132;		/*  Transmit Collision Count */
//	private static final int PP_LineST = 0x0134;	/*  Line State Register */
	private static final int PP_SelfST = 0x0136;	/*  Self State register */
	private static final int PP_BusST = 0x0138;		/*  Bus Status */
//	private static final int PP_TDR = 0x013C;		/*  Time Domain Reflectometry */
//	private static final int PP_AutoNegST = 0x013E;	/*  Auto Neg Status */
//	private static final int PP_TxCommand = 0x0144;	/*  Tx Command */
//	private static final int PP_TxLength = 0x0146;	/*  Tx Length */
//	private static final int PP_LAF = 0x0150;		/*  Hash Table */
	private static final int PP_IA = 0x0158;		/*  Physical Address Register */

//	private static final int PP_RxStatus = 0x0400;	/*  Receive start of frame */
//	private static final int PP_RxLength = 0x0402;	/*  Receive Length of frame */
//	private static final int PP_RxFrame = 0x0404;	/*  Receive frame pointer */
//	private static final int PP_TxFrame = 0x0A00;	/*  Transmit frame pointer */

//	private static final int ADD_MASK = 0x3000;		/*  Mask it use of the ADD_PORT register */
//	private static final int ADD_SIG = 0x3000;		/*  Expected ID signature */

/*  Mask to find out the types of  registers */
//	private static final int REG_TYPE_MASK = 0x001F;

/*  Defines Control/Config register quintuplet numbers */
//	private static final int RX_BUF_CFG = 0x0003;
//	private static final int RX_CONTROL = 0x0005;
//	private static final int TX_CFG = 0x0007;
//	private static final int TX_COMMAND = 0x0009;
//	private static final int BUF_CFG = 0x000B;
//	private static final int LINE_CONTROL = 0x0013;
//	private static final int SELF_CONTROL = 0x0015;
//	private static final int BUS_CONTROL = 0x0017;
//	private static final int TEST_CONTROL = 0x0019;

/*  Defines Status/Count registers quintuplet numbers */
//	private static final int RX_EVENT = 0x0004;
//	private static final int TX_EVENT = 0x0008;
//	private static final int BUF_EVENT = 0x000C;
//	private static final int RX_MISS_COUNT = 0x0010;
//	private static final int TX_COL_COUNT = 0x0012;
//	private static final int LINE_STATUS = 0x0014;
//	private static final int SELF_STATUS = 0x0016;
//	private static final int BUS_STATUS = 0x0018;
//	private static final int TDR = 0x001C;

/* PP_RxCFG - Receive  Configuration and Interrupt Mask bit definition -  Read/write */
	private static final int SKIP_1 = 0x0040;
//	private static final int RX_STREAM_ENBL = 0x0080;
	private static final int RX_OK_ENBL = 0x0100;
//	private static final int RX_DMA_ONLY = 0x0200;
//	private static final int AUTO_RX_DMA = 0x0400;
//	private static final int BUFFER_CRC = 0x0800;
	private static final int RX_CRC_ERROR_ENBL = 0x1000;
//	private static final int RX_RUNT_ENBL = 0x2000;
//	private static final int RX_EXTRA_DATA_ENBL = 0x4000;

/* PP_RxCTL - Receive Control bit definition - Read/write */
//	private static final int RX_IA_HASH_ACCEPT = 0x0040;
//	private static final int RX_PROM_ACCEPT = 0x0080;
	private static final int RX_OK_ACCEPT = 0x0100;
//	private static final int RX_MULTCAST_ACCEPT = 0x0200;
	private static final int RX_IA_ACCEPT = 0x0400;
	private static final int RX_BROADCAST_ACCEPT = 0x0800;
//	private static final int RX_BAD_CRC_ACCEPT = 0x1000;
//	private static final int RX_RUNT_ACCEPT = 0x2000;
//	private static final int RX_EXTRA_DATA_ACCEPT = 0x4000;
//	private static final int RX_ALL_ACCEPT = (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT);
/*  Default receive mode - individually addressed, broadcast, and error free */
	private static final int DEF_RX_ACCEPT = (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT);

/* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
	private static final int TX_LOST_CRS_ENBL = 0x0040;
	private static final int TX_SQE_ERROR_ENBL = 0x0080;
	private static final int TX_OK_ENBL = 0x0100;
	private static final int TX_LATE_COL_ENBL = 0x0200;
	private static final int TX_JBR_ENBL = 0x0400;
	private static final int TX_ANY_COL_ENBL = 0x0800;
	private static final int TX_16_COL_ENBL = 0x8000;

/* PP_TxCMD - Transmit Command bit definition - Read-only */
//	private static final int TX_START_4_BYTES = 0x0000;
//	private static final int TX_START_64_BYTES = 0x0040;
//	private static final int TX_START_128_BYTES = 0x0080;
//	private static final int TX_START_ALL_BYTES = 0x00C0;
//	private static final int TX_FORCE = 0x0100;
//	private static final int TX_ONE_COL = 0x0200;
//	private static final int TX_TWO_PART_DEFF_DISABLE = 0x0400;
//	private static final int TX_NO_CRC = 0x1000;
//	private static final int TX_RUNT = 0x2000;

/* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */
//	private static final int GENERATE_SW_INTERRUPT = 0x0040;
//	private static final int RX_DMA_ENBL = 0x0080;
	private static final int READY_FOR_TX_ENBL = 0x0100;
	private static final int TX_UNDERRUN_ENBL = 0x0200;
//	private static final int RX_MISS_ENBL = 0x0400;
//	private static final int RX_128_BYTE_ENBL = 0x0800;
	private static final int TX_COL_COUNT_OVRFLOW_ENBL = 0x1000;
	private static final int RX_MISS_COUNT_OVRFLOW_ENBL = 0x2000;
//	private static final int RX_DEST_MATCH_ENBL = 0x8000;

/* PP_LineCTL - Line Control bit definition - Read/write */
	private static final int SERIAL_RX_ON = 0x0040;
	private static final int SERIAL_TX_ON = 0x0080;
//	private static final int AUI_ONLY = 0x0100;
//	private static final int AUTO_AUI_10BASET = 0x0200;
//	private static final int MODIFIED_BACKOFF = 0x0800;
//	private static final int NO_AUTO_POLARITY = 0x1000;
//	private static final int TWO_PART_DEFDIS = 0x2000;
//	private static final int LOW_RX_SQUELCH = 0x4000;

/* PP_SelfCTL - Software Self Control bit definition - Read/write */
//	private static final int POWER_ON_RESET = 0x0040;
//	private static final int SW_STOP = 0x0100;
//	private static final int SLEEP_ON = 0x0200;
//	private static final int AUTO_WAKEUP = 0x0400;
//	private static final int HCB0_ENBL = 0x1000;
//	private static final int HCB1_ENBL = 0x2000;
//	private static final int HCB0 = 0x4000;
//	private static final int HCB1 = 0x8000;

/* PP_BusCTL - ISA Bus Control bit definition - Read/write */
//	private static final int RESET_RX_DMA = 0x0040;
//	private static final int MEMORY_ON = 0x0400;
//	private static final int DMA_BURST_MODE = 0x0800;
	private static final int IO_CHANNEL_READY_ON = 0x1000;
//	private static final int RX_DMA_SIZE_64K = 0x2000;
//	private static final int ENABLE_IRQ = 0x8000;

/* PP_TestCTL - Test Control bit definition - Read/write */
//	private static final int LINK_OFF = 0x0080;
//	private static final int ENDEC_LOOPBACK = 0x0200;
//	private static final int AUI_LOOPBACK = 0x0400;
//	private static final int BACKOFF_OFF = 0x0800;
//	private static final int FDX_8900 = 0x4000;
//	private static final int FAST_TEST = 0x8000;

/* PP_RxEvent - Receive Event Bit definition - Read-only */
//	private static final int RX_IA_HASHED = 0x0040;
//	private static final int RX_DRIBBLE = 0x0080;
	private static final int RX_OK = 0x0100;
//	private static final int RX_HASHED = 0x0200;
//	private static final int RX_IA = 0x0400;
//	private static final int RX_BROADCAST = 0x0800;
//	private static final int RX_CRC_ERROR = 0x1000;
//	private static final int RX_RUNT = 0x2000;
//	private static final int RX_EXTRA_DATA = 0x4000;

//	private static final int HASH_INDEX_MASK = 0x0FC00;

/* PP_TxEvent - Transmit Event Bit definition - Read-only */
	private static final int TX_LOST_CRS = 0x0040;
	private static final int TX_SQE_ERROR = 0x0080;
	private static final int TX_OK = 0x0100;
	private static final int TX_LATE_COL = 0x0200;
//	private static final int TX_JBR = 0x0400;
	private static final int TX_16_COL = 0x8000;
//	private static final int TX_SEND_OK_BITS = (TX_OK|TX_LOST_CRS);
//	private static final int TX_COL_COUNT_MASK = 0x7800;

/* PP_BufEvent - Buffer Event Bit definition - Read-only */
//	private static final int SW_INTERRUPT = 0x0040;
//	private static final int RX_DMA = 0x0080;
	private static final int READY_FOR_TX = 0x0100;
	private static final int TX_UNDERRUN = 0x0200;
//	private static final int RX_MISS = 0x0400;
//	private static final int RX_128_BYTE = 0x0800;
//	private static final int TX_COL_OVRFLW = 0x1000;
//	private static final int RX_MISS_OVRFLW = 0x2000;
//	private static final int RX_DEST_MATCH = 0x8000;

/* PP_LineST - Ethernet Line Status bit definition - Read-only */
//	private static final int LINK_OK = 0x0080;
//	private static final int AUI_ON = 0x0100;
//	private static final int TENBASET_ON = 0x0200;
//	private static final int POLARITY_OK = 0x1000;
//	private static final int CRS_OK = 0x4000;

/* PP_SelfST - Chip Software Status bit definition */
//	private static final int ACTIVE_33V = 0x0040;
	private static final int INIT_DONE = 0x0080;
//	private static final int SI_BUSY = 0x0100;
//	private static final int EEPROM_PRESENT = 0x0200;
//	private static final int EEPROM_OK = 0x0400;
//	private static final int EL_PRESENT = 0x0800;
//	private static final int EE_SIZE_64 = 0x1000;

/* PP_BusST - ISA Bus Status bit definition */
//	private static final int TX_BID_ERROR = 0x0080;
	private static final int READY_FOR_TX_NOW = 0x0100;

/* PP_AutoNegCTL - Auto Negotiation Control bit definition */
//	private static final int RE_NEG_NOW = 0x0040;
//	private static final int ALLOW_FDX = 0x0080;
//	private static final int AUTO_NEG_ENABLE = 0x0100;
//	private static final int NLP_ENABLE = 0x0200;
//	private static final int FORCE_FDX = 0x8000;
//	private static final int AUTO_NEG_BITS = (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE);
//	private static final int AUTO_NEG_MASK = (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW);

/* PP_AutoNegST - Auto Negotiation Status bit definition */
//	private static final int AUTO_NEG_BUSY = 0x0080;
//	private static final int FLP_LINK = 0x0100;
//	private static final int FLP_LINK_GOOD = 0x0800;
//	private static final int LINK_FAULT = 0x1000;
//	private static final int HDX_ACTIVE = 0x4000;
//	private static final int FDX_ACTIVE = 0x8000;

/*  The following block defines the ISQ event types */
	private static final int ISQ_RECEIVER_EVENT = 0x04;
	private static final int ISQ_TRANSMITTER_EVENT = 0x08;
	private static final int ISQ_BUFFER_EVENT = 0x0c;
//	private static final int ISQ_RX_MISS_EVENT = 0x10;
//	private static final int ISQ_TX_COL_EVENT = 0x12;