cs8900.java

Java Op Processor java vhdl processor

	private static final int ISQ_RECEIVER_EVENT = 0x04;
	private static final int ISQ_TRANSMITTER_EVENT = 0x08;
	private static final int ISQ_BUFFER_EVENT = 0x0c;
	private static final int ISQ_RX_MISS_EVENT = 0x10;
	private static final int ISQ_TX_COL_EVENT = 0x12;

	private static final int ISQ_EVENT_MASK = 0x003F;   /*  ISQ mask to find out type of event */
	private static final int ISQ_HIST = 16;		/*  small history buffer */
	private static final int AUTOINCREMENT = 0x8000;	/*  Bit mask to set bit-15 for autoincrement */

	private static final int TXRXBUFSIZE = 0x0600;
	private static final int RXDMABUFSIZE = 0x8000;
	private static final int RXDMASIZE = 0x4000;
	private static final int TXRX_LENGTH_MASK = 0x07FF;

/*  rx options bits */
	private static final int RCV_WITH_RXON	= 1;       /*  Set SerRx ON */
	private static final int RCV_COUNTS	= 2;       /*  Use Framecnt1 */
	private static final int RCV_PONG	= 4;       /*  Pong respondent */
	private static final int RCV_DONG	= 8;       /*  Dong operation */
	private static final int RCV_POLLING	= 0x10;	/*  Poll RxEvent */
	private static final int RCV_ISQ		= 0x20;	/*  Use ISQ, int */
	private static final int RCV_AUTO_DMA	= 0x100;	/*  Set AutoRxDMAE */
	private static final int RCV_DMA		= 0x200;	/*  Set RxDMA only */
	private static final int RCV_DMA_ALL	= 0x400;	/*  Copy all DMA'ed */
	private static final int RCV_FIXED_DATA	= 0x800;	/*  Every frame same */
	private static final int RCV_IO		= 0x1000;	/*  Use ISA IO only */
	private static final int RCV_MEMORY	= 0x2000;	/*  Use ISA Memory */

	private static final int RAM_SIZE	= 0x1000;       /*  The card has 4k bytes or RAM */
	private static final int PKT_START = PP_TxFrame;  /*  Start of packet RAM */

	private static final int RX_FRAME_PORT	= 0x0000;
	private static final int TX_FRAME_PORT = RX_FRAME_PORT;
	private static final int TX_CMD_PORT	= 0x0004;
	private static final int TX_NOW		= 0x0000;       /*  Tx packet after   5 bytes copied */
	private static final int TX_AFTER_381	= 0x0040;       /*  Tx packet after 381 bytes copied */
	private static final int TX_AFTER_ALL	= 0x00c0;       /*  Tx packet after all bytes copied */
	private static final int TX_LEN_PORT	= 0x0006;
	private static final int ISQ_PORT	= 0x0008;
	private static final int ADD_PORT	= 0x000A;
	private static final int DATA_PORT	= 0x000C;


/*  Receive Header */
/*  Description of header of each packet in receive area of memory */
	private static final int RBUF_EVENT_LOW	= 0;   /*  Low byte of RxEvent - status of received frame */
	private static final int RBUF_EVENT_HIGH	= 1;   /*  High byte of RxEvent - status of received frame */
	private static final int RBUF_LEN_LOW	= 2;   /*  Length of received data - low byte */
	private static final int RBUF_LEN_HI	= 3;   /*  Length of received data - high byte */
	private static final int RBUF_HEAD_LEN	= 4;   /*  Length of this header */

	private static final int CHIP_READ = 0x1;   /*  Used to mark state of the repins code (chip or dma) */
	private static final int DMA_READ = 0x2;   /*  Used to mark state of the repins code (chip or dma) */


	private static final int IMM_BIT = 0x0040;		/*  ignore missing media	 */

	private static final int A_CNF_10B_T = 0x0001;
	private static final int A_CNF_AUI = 0x0002;
	private static final int A_CNF_10B_2 = 0x0004;
	private static final int A_CNF_MEDIA_TYPE = 0x0060;
	private static final int A_CNF_MEDIA_AUTO = 0x0000;
	private static final int A_CNF_MEDIA_10B_T = 0x0020;
	private static final int A_CNF_MEDIA_AUI = 0x0040;
	private static final int A_CNF_MEDIA_10B_2 = 0x0060;
	private static final int A_CNF_DC_DC_POLARITY = 0x0080;
	private static final int A_CNF_NO_AUTO_POLARITY = 0x2000;
	private static final int A_CNF_LOW_RX_SQUELCH = 0x4000;
	private static final int A_CNF_EXTND_10B_2 = 0x8000;

	private static final int PACKET_PAGE_OFFSET = 0x8;

	private static final int BIT0 = 1;
	private static final int BIT15 = 0x8000;


//
//	ISA bus handling
//
	private static final int IO_CTRL = 5;
	private static final int IO_DATA = 6;

	private static final int ISA_RESET = 0x20;
	private static final int ISA_RD = 0x40;
	private static final int ISA_WR = 0x80;
	private static final int ISA_DIR = 0x100;	// means driving out
/*
	VHDL definition:

	isa_a <= din(4 downto 0);
	isa_reset <= din(5);
	isa_nior <= not din(6);
	isa_niow <= not din(7);
	isa_dir <= din(8);
*/


/**
*	reset isa bus
*/
	private static void resetIsa() {

		Native.wr(ISA_RESET, IO_CTRL);				// isa bus reset
		Thread.sleep(5);
		Native.wr(0, IO_CTRL);					// disable reset
		Thread.sleep(5);
	}

/**
*	'ISA Bus' io read cycle 2x8 bit.
*/
	private static int readWord(int port) {

		Native.wr(port, IO_CTRL);				// port
		Native.wr(port | ISA_RD, IO_CTRL);		// nior low
		int ret = Native.rd(IO_DATA);			// read data
		Native.wr(port, IO_CTRL);				// nior high again
		++port;
		Native.wr(port, IO_CTRL);				// port
		Native.wr(port | ISA_RD, IO_CTRL);		// nior low
		ret += Native.rd(IO_DATA)<<8;			// read data
		Native.wr(port, IO_CTRL);				// nior high again

		return ret;
	}

/**
*	'ISA Bus' io read cycle 2x8 bit with high byte first.
*/
	private static int readWordHighFirst(int port) {

		++port;
		Native.wr(port, IO_CTRL);				// addr
		Native.wr(port | ISA_RD, IO_CTRL);		// nior low
		int ret = Native.rd(IO_DATA)<<8;		// read data
		Native.wr(port, IO_CTRL);				// nior high again
		--port;
		Native.wr(port, IO_CTRL);				// addr
		Native.wr(port | ISA_RD, IO_CTRL);		// nior low
		ret += Native.rd(IO_DATA)&0xff;			// read data
		Native.wr(port, IO_CTRL);				// nior high again

		return ret;
	}

/**
*	'ISA Bus' io write cycle 2x8 bit.
*	first low byte than high byte at higher address.
*/
	private static void writeWord(int port, int value) {

		Native.wr(value, IO_DATA);					// value in buffer
		Native.wr(port | ISA_DIR, IO_CTRL);			// port and drive value out
		Native.wr(port | ISA_WR | ISA_DIR, IO_CTRL);	// niow low
		Native.wr(port | ISA_DIR, IO_CTRL);			// niow high again
		++port;
		Native.wr(value>>8, IO_DATA);				// value in buffer
		Native.wr(port | ISA_DIR, IO_CTRL);			// port and drive value out
		Native.wr(port | ISA_WR | ISA_DIR, IO_CTRL);	// niow low
		Native.wr(port | ISA_DIR, IO_CTRL);			// niow high again
		Native.wr(port, IO_CTRL);					// disable dout
	}


	private static int readReg(int reg) {
		writeWord(ADD_PORT, reg);
		return readWord(DATA_PORT);
	}
	private static void writeReg(int reg, int value) {
		writeWord(ADD_PORT, reg);
		writeWord(DATA_PORT, value);
	}

/**
*	write ethernet header.
*/
	// private static void writeHead(int txAddrHi, int txAddrLo, int txType) {
	private static void writeHead(Packet p) {

		int i, val;

		p.llh[3] = mac_hi;
		p.llh[4] = mac_mid;
		p.llh[5] = mac_low;
		for (i=0; i<ETH_HLEN/2; ++i) {

			val = p.llh[i];
			Native.wr(val>>>8, IO_DATA);							// value in buffer
			Native.wr(TX_FRAME_PORT | ISA_DIR, IO_CTRL);			// port and drive value out
			Native.wr(TX_FRAME_PORT | ISA_WR | ISA_DIR, IO_CTRL);	// niow low
			Native.wr(TX_FRAME_PORT | ISA_DIR, IO_CTRL);			// niow high again
			Native.wr(val, IO_DATA);								// value in buffer
			Native.wr(TX_FRAME_PORT+1 | ISA_DIR, IO_CTRL);			// port and drive value out
			Native.wr(TX_FRAME_PORT+1 | ISA_WR | ISA_DIR, IO_CTRL);	// niow low
			Native.wr(TX_FRAME_PORT+1 | ISA_DIR, IO_CTRL);			// niow high again
		}
		Native.wr(TX_FRAME_PORT+1, IO_CTRL);						// disable dout
	}
/**
*	write tx data.
*/
	private static void writeData(Packet p) {

		int i, val;
		int[] buf = p.buf;
		int length = p.len;

		if ((length & 1) == 1) ++length;		// even bytes
		val = 0;

		for (i=0; i<length; i+=2) {

			if ((i & 2) != 0) {
				val <<= 16;
			} else {
				val = buf[(i>>2)];
			}

			Native.wr(val>>>24, IO_DATA);							// value in buffer
			Native.wr(TX_FRAME_PORT | ISA_DIR, IO_CTRL);			// port and drive value out
			Native.wr(TX_FRAME_PORT | ISA_WR | ISA_DIR, IO_CTRL);	// niow low
			Native.wr(TX_FRAME_PORT | ISA_DIR, IO_CTRL);			// niow high again
			Native.wr(val>>>16, IO_DATA);							// value in buffer
			Native.wr(TX_FRAME_PORT+1 | ISA_DIR, IO_CTRL);			// port and drive value out
			Native.wr(TX_FRAME_PORT+1 | ISA_WR | ISA_DIR, IO_CTRL);	// niow low
			Native.wr(TX_FRAME_PORT+1 | ISA_DIR, IO_CTRL);			// niow high again
		}
		Native.wr(TX_FRAME_PORT+1, IO_CTRL);						// disable dout
	}

/**
*	read ethernet header.
*/
	private static void readHead(Packet p) {

		int i, val;
		int[] buf = p.llh;

		for (i=0; i<ETH_HLEN/2; ++i) {

			// be careful: intel byte order!
			Native.wr(RX_FRAME_PORT, IO_CTRL);				// port
			Native.wr(RX_FRAME_PORT | ISA_RD, IO_CTRL);		// nior low
			val = Native.rd(IO_DATA)<<8;					// read data (second byte)
			Native.wr(RX_FRAME_PORT, IO_CTRL);				// nior high again
			Native.wr(RX_FRAME_PORT+1, IO_CTRL);			// port
			Native.wr(RX_FRAME_PORT+1 | ISA_RD, IO_CTRL);	// nior low
			buf[i] = val + Native.rd(IO_DATA);				// read data (first byte)
			Native.wr(RX_FRAME_PORT+1, IO_CTRL);			// nior high again
		}
	}
/**
*	read rx data.
*/
	private static void readData(Packet p) {

		int i, val;
		int length = p.len;
		int[] buf = p.buf;

		if ((length & 1) != 0) ++length;		// even bytes
		val = 0;

		for (i=0; i<length; i+=2) {

			Native.wr(RX_FRAME_PORT, IO_CTRL);				// port
			Native.wr(RX_FRAME_PORT | ISA_RD, IO_CTRL);		// nior low
			val += Native.rd(IO_DATA)<<8;					// read data
			Native.wr(RX_FRAME_PORT, IO_CTRL);				// nior high again
			Native.wr(RX_FRAME_PORT+1, IO_CTRL);			// port
			Native.wr(RX_FRAME_PORT+1 | ISA_RD, IO_CTRL);	// nior low
			val += Native.rd(IO_DATA);						// read data
			Native.wr(RX_FRAME_PORT+1, IO_CTRL);			// nior high again

			if ((i & 2) != 0) {
				buf[i>>2] = val;
				val = 0;
			} else {
				val <<= 16;
			}
		}
		if ((length & 2) != 0) {				// length is not a multiple of 4
			buf[length>>2] = val;
		}
	}

/**
*	allocate buffer and reset chip.
*/
	public static void init(int[] mac) {

		txFree = true;

		eth = new int[6];
		for (int i=0; i<6; ++i) eth[i] = mac[i];
		// intel byte order !!!
		mac_hi = mac[0]<<8 | mac[1];
		mac_mid = mac[2]<<8 | mac[3];
		mac_low = mac[4]<<8 | mac[5];

		tx_packets = 0;
		tx_bytes = 0;
		collisions = 0;

		rx_packets = 0;
		rx_bytes = 0;
		rx_dropped = 0;
		multicast = 0;

		tx_errors = 0;
		tx_aborted_errors = 0;
		tx_carrier_errors = 0;
		tx_fifo_errors = 0;
		tx_heartbeat_errors = 0;
		tx_window_errors = 0;

		rx_errors = 0;
		rx_over_errors = 0;
		rx_length_errors = 0;
		rx_frame_errors = 0;
		rx_crc_errors = 0;
		rx_missed_errors = 0;