rtl8019.java

Java Op Processor java vhdl processor

package tcpip;

/**
*	Eth.java: A general non-shared-memory NS8390 ethernet driver.
*
*	Adapted by Martin Schoeberl ([e-mail])
*
*	from by Donald Becker's Linux driver (8390.h, 8390.c and ne.c)
*
*   Copyright 1993 United States Government as represented by the
*   Director, National Security Agency.
*
*   This software may be used and distributed according to the terms
*   of the GNU General Public License, incorporated herein by reference.
*
*   The author may be reached as [e-mail], or C/O
*   Scyld Computing Corporation, 410 Severn Ave., Suite 210, Annapolis MD 21403
*
*   This driver should work with many programmed-I/O 8390-based ethernet
*   boards.
*
*	Martin Schoeberl:
*
*	NS8390x, RTL8019AS are used in 8 Bit mode for simpler connection to an
*	embedded system.
*
*   Changelog:
*		2002-03-15	ARP works!
*
*
*/

public class RTL8019 {

	public static final int IO_ISA_CTRL = 5;
	public static final int IO_ISA_DATA = 6;

	public static final int ISA_RESET = 0x20;
	public static final int ISA_RD = 0x40;
	public static final int ISA_WR = 0x80;
	public static final int ISA_DIR = 0x100;
/*
			isa_a <= din(4 downto 0);
			isa_reset <= din(5);
			isa_nior <= not din(6);
			isa_niow <= not din(7);
			isa_dir <= din(8);
			isa_nc <= '0';
*/

	private static int[] serBuf;			// a generic buffer
	private static final int MAX_SER = 32;
	private static final int BUF_LEN = 6*256;
	private static int[] buf;				// send AND receive buffer
	private static int[] eth;				// own ethernet address
	private static int[] ip;				// own ip address

	private static int tx_start_page;
	private static int rx_start_page;
	private static int stop_page;
	private static int current_page;

	private static int tx1, tx2;
	private static boolean txing;

/* some statistics */
	private static int tx_packets;
	private static int tx_bytes;
	private static int collisions;

	private static int rx_packets;
	private static int rx_bytes;
	private static int rx_dropped;
	private static int multicast;

	private static int tx_errors;
	private static int tx_aborted_errors;
	private static int tx_carrier_errors;
	private static int tx_fifo_errors;
	private static int tx_heartbeat_errors;
	private static int tx_window_errors;

	private static int rx_errors;
	private static int rx_over_errors;
	private static int rx_length_errors;
	private static int rx_frame_errors;
	private static int rx_crc_errors;
	private static int rx_missed_errors;
	private static int rx_fifo_errors;

/************/

/* Generic NS8390 register definitions. */
/* This file is part of Donald Becker's 8390 drivers, and is distributed
   under the same license. 
   Some of these names and comments originated from the Crynwr
   packet drivers, which are distributed under the GPL. */


//#define ETHER_ADDR_LEN 6

/* The 8390 specific per-packet-header format. */
//struct e8390_pkt_hdr {
//  unsigned char status; /* status */
//  unsigned char next;   /* pointer to next packet. */
//  unsigned short count; /* header + packet length in bytes */
//};


/* Some generic ethernet register configurations. */
	public static final int E8390_TX_IRQ_MASK = 0xa;	/* For register EN0_ISR */
	public static final int E8390_RX_IRQ_MASK = 0x5;
	public static final int E8390_RXCONFIG = 0x4;	/* EN0_RXCR: broadcasts, no multicast,errors */
	public static final int E8390_RXOFF = 0x20;	/* EN0_RXCR: Accept no packets */
	public static final int E8390_TXCONFIG = 0x00;	/* EN0_TXCR: Normal transmit mode */
	public static final int E8390_TXOFF = 0x02;	/* EN0_TXCR: Transmitter off */

/*  Register accessed at EN_CMD, the 8390 base addr.  */
	public static final int E8390_STOP = 0x01;	/* Stop and reset the chip */
	public static final int E8390_START = 0x02;	/* Start the chip, clear reset */
	public static final int E8390_TRANS = 0x04;	/* Transmit a frame */
	public static final int E8390_RREAD = 0x08;	/* Remote read */
	public static final int E8390_RWRITE = 0x10;	/* Remote write  */
	public static final int E8390_SEND = 0x18;	/* 'Send Packet' */
	public static final int E8390_NODMA = 0x20;	/* Remote DMA */
	public static final int E8390_PAGE0 = 0x00;	/* Select page chip registers */
	public static final int E8390_PAGE1 = 0x40;	/* using the two high-order bits */
	public static final int E8390_PAGE2 = 0x80;	/* Page 3 is invalid. */

	public static final int E8390_CMD = 0x00;  /* The command register (for all pages) */
/* Page 0 register offsets. */
	public static final int EN0_CLDALO = 0x01;	/* Low byte of current local dma addr  RD */
	public static final int EN0_STARTPG = 0x01;	/* Starting page of ring bfr WR */
	public static final int EN0_CLDAHI = 0x02;	/* High byte of current local dma addr  RD */
	public static final int EN0_STOPPG = 0x02;	/* Ending page +1 of ring bfr WR */
	public static final int EN0_BOUNDARY = 0x03;	/* Boundary page of ring bfr RD WR */
	public static final int EN0_TSR = 0x04;		/* Transmit status reg RD */
	public static final int EN0_TPSR = 0x04;	/* Transmit starting page WR */
	public static final int EN0_NCR = 0x05;		/* Number of collision reg RD */
	public static final int EN0_TCNTLO = 0x05;	/* Low  byte of tx byte count WR */
	public static final int EN0_FIFO = 0x06;	/* FIFO RD */
	public static final int EN0_TCNTHI = 0x06;	/* High byte of tx byte count WR */
	public static final int EN0_ISR = 0x07;		/* Interrupt status reg RD WR */
	public static final int EN0_CRDALO = 0x08;	/* low byte of current remote dma address RD */
	public static final int EN0_RSARLO = 0x08;	/* Remote start address reg 0 */
	public static final int EN0_CRDAHI = 0x09;	/* high byte, current remote dma address RD */
	public static final int EN0_RSARHI = 0x09;	/* Remote start address reg 1 */
	public static final int EN0_RCNTLO = 0x0a;	/* Remote byte count reg WR */
	public static final int EN0_RCNTHI = 0x0b;	/* Remote byte count reg WR */
	public static final int EN0_RSR = 0x0c;		/* rx status reg RD */
	public static final int EN0_RXCR = 0x0c;	/* RX configuration reg WR */
	public static final int EN0_TXCR = 0x0d;	/* TX configuration reg WR */
	public static final int EN0_COUNTER0 = 0x0d;	/* Rcv alignment error counter RD */
	public static final int EN0_DCFG = 0x0e;	/* Data configuration reg WR */
	public static final int EN0_COUNTER1 = 0x0e;	/* Rcv CRC error counter RD */
	public static final int EN0_IMR = 0x0f;		/* Interrupt mask reg WR */
	public static final int EN0_COUNTER2 = 0x0f;	/* Rcv missed frame error counter RD */

/* Bits in EN0_ISR - Interrupt status register */
	public static final int ENISR_RX = 0x01;	/* Receiver, no error */
	public static final int ENISR_TX = 0x02;	/* Transmitter, no error */
	public static final int ENISR_RX_ERR = 0x04;	/* Receiver, with error */
	public static final int ENISR_TX_ERR = 0x08;	/* Transmitter, with error */
	public static final int ENISR_OVER = 0x10;	/* Receiver overwrote the ring */
	public static final int ENISR_COUNTERS = 0x20;	/* Counters need emptying */
	public static final int ENISR_RDC = 0x40;	/* remote dma complete */
	public static final int ENISR_RESET = 0x80;	/* Reset completed */
	public static final int ENISR_ALL = 0x3f;	/* Interrupts we will enable */

/* Bits in EN0_DCFG - Data config register */
	public static final int ENDCFG_WTS = 0x01;	/* word transfer mode selection */
	public static final int ENDCFG_BOS = 0x02;	/* byte order selection */

/* Page 1 register offsets. */
	public static final int EN1_PHYS = 0x01;	/* This board's physical enet addr RD WR */
//	public static final int EN1_PHYS_SHIFT(i)  (i+1) /* Get and set mac address */
	public static final int EN1_CURPAG = 0x07;	/* Current memory page RD WR */
	public static final int EN1_MULT = 0x08;	/* Multicast filter mask array (8 bytes) RD WR */
//	public static final int EN1_MULT_SHIFT(i)  (8+i) /* Get and set multicast filter */

/* Bits in received packet status byte and EN0_RSR*/
	public static final int ENRSR_RXOK = 0x01;	/* Received a good packet */
	public static final int ENRSR_CRC = 0x02;	/* CRC error */
	public static final int ENRSR_FAE = 0x04;	/* frame alignment error */
	public static final int ENRSR_FO = 0x08;	/* FIFO overrun */
	public static final int ENRSR_MPA = 0x10;	/* missed pkt */
	public static final int ENRSR_PHY = 0x20;	/* physical/multicast address */
	public static final int ENRSR_DIS = 0x40;	/* receiver disable. set in monitor mode */
	public static final int ENRSR_DEF = 0x80;	/* deferring */

/* Transmitted packet status, EN0_TSR. */
	public static final int ENTSR_PTX = 0x01;	/* Packet transmitted without error */
	public static final int ENTSR_ND  = 0x02;	/* The transmit wasn't deferred. */
	public static final int ENTSR_COL = 0x04;	/* The transmit collided at least once. */
	public static final int ENTSR_ABT = 0x08;	/* The transmit collided 16 times, and was deferred. */
	public static final int ENTSR_CRS = 0x10;	/* The carrier sense was lost. */
	public static final int ENTSR_FU  = 0x20;	/* A "FIFO underrun" occurred during transmit. */
	public static final int ENTSR_CDH = 0x40;	/* The collision detect "heartbeat" signal was lost. */
	public static final int ENTSR_OWC = 0x80;	/* There was an out-of-window collision. */

/* The maximum number of 8390 interrupt service routines called per IRQ. */
	//public static final int MAX_SERVICE = 12;
	public static final int MAX_SERVICE = 1;	// only one buffer

/* The maximum time waited before assuming a Tx failed. (20ms) */
	public static final int TX_TIMEOUT = 20;

/************/
/* from ne.c */
	public static final int NE_DATAPORT = 0x10;	/* NatSemi-defined port window offset. */
	public static final int NE_RESET    = 0x1f;	/* Issue a read to reset, a write to clear. */

// really 0x40 ????? or 0x60 !!! --- byte versus word access ???
//	public static final int NE1SM_START_PG = 0x20;	/* First page of TX buffer */
//	public static final int NE1SM_STOP_PG  = 0x40;	/* Last page +1 of RX ring */

	public static final int NE_START_PG = 0x40;	/* First page of TX buffer */
	public static final int NE_STOP_PG  = 0x60;	/* Last page +1 of RX ring */
/* Should always use two Tx slots to get back-to-back transmits. */
	public static final int TX_PAGES = 12;		// two transmit buffers a 6 pages

/* from ../include/linux/if_ether.h */
	public static final int ETH_ALEN = 6;		/* Octets in one ethernet addr	 */
	public static final int ETH_HLEN = 14;		/* Total octets in header.	 */
	public static final int ETH_ZLEN = 60;		/* Min. octets in frame sans FCS */
	public static final int ETH_DATA_LEN = 1500;		/* Max. octets in payload	 */
	public static final int ETH_FRAME_LEN = 1514;		/* Max. octets in frame sans FCS */



	private static int rcv_len;
/**
*	test main.
*/
	public static void main(String[] args) {

		buf = new int[BUF_LEN];
		serBuf = new int[MAX_SER];
		eth = new int[6];
		ip = new int[4];
		ip[0] = 192;
		ip[1] = 168;
		ip[2] = 0;
		ip[3] = 4;
		int i, j;

		rcv_len = 0;

		TcpIp.init();
		Timer.init();			// just for the watch dog

		if (!init()) {
			wrSer('f');
			for (;;) ;
		}

		int old_cur = -1;

		for (;;) {
			// are there unread pages?
			wr(E8390_NODMA+E8390_PAGE1+E8390_START, E8390_CMD);
			i = rd(EN1_CURPAG);
			wr(E8390_NODMA+E8390_PAGE0+E8390_START, E8390_CMD);
			j = rd(EN0_BOUNDARY) + 1;

			if (i!=old_cur) {
				old_cur = i;
				wrSer('c');
				wrSer(' ');
				hexVal(i);
				wrSer('\n');
			}
			if (rd(EN0_ISR) != 0) {		// activ poll
				wrSer('\n');
				wrSer('i');
				wrSer(' ');
				interrupt();
			} else if (i!=j) {			// read more pages
				receive();
			}
			if (rcv_len!=0) {
				process();
			}

			Timer.wd();
		}
	}

	private static void process() {

		int i;
		int len;

		i = (buf[12]<<8) + buf[13];
		if (i == 0x0806) {					// ARP type
			arp();
		} else if (i == 0x0800) {			// IP type
			len = TcpIp.receive(buf, ETH_HLEN, rcv_len-ETH_HLEN);
			if (len!=0) {
				for (i=0; i<6; ++i) {
					buf[0+i] = buf[6+i];	// old src->dest
					buf[6+i] = eth[i];		// src
				}
/*
wrSer('I');
wrSer(' ');
for (i=0; i<ETH_HLEN+len; ++i) hexVal(buf[i]);
wrSer('\n');
*/
				startXmit(buf, ETH_HLEN+len);		// send back changed packet
			}
		}
		// ignore
		rcv_len = 0;
	}

	private static void arp() {

		int i;

		wrSer('A');

		intVal(buf[38]);
		intVal(buf[39]);
		intVal(buf[40]);
		intVal(buf[41]);

		if (buf[38]==ip[0] &&
			buf[39]==ip[1] &&
			buf[40]==ip[2] &&
			buf[41]==ip[3]) {


/*
    Ethernet packet data:
	16.bit: (ar$hrd) Hardware address space (e.g., Ethernet,
			 Packet Radio Net.)
	16.bit: (ar$pro) Protocol address space.  For Ethernet
			 hardware, this is from the set of type
			 fields ether_typ$<protocol>.
	 8.bit: (ar$hln) byte length of each hardware address
	 8.bit: (ar$pln) byte length of each protocol address
	16.bit: (ar$op)  opcode (ares_op$REQUEST | ares_op$REPLY)
	nbytes: (ar$sha) Hardware address of sender of this
			 packet, n from the ar$hln field.
	mbytes: (ar$spa) Protocol address of sender of this
			 packet, m from the ar$pln field.
	nbytes: (ar$tha) Hardware address of target of this
			 packet (if known).
	mbytes: (ar$tpa) Protocol address of target.
*/
			/*
			Swap hardware and protocol fields, putting the local
	    	hardware and protocol addresses in the sender fields.
			*/
			swapAdr();

			/*
			Set the ar$op field to ares_op$REPLY
			*/
			buf[21] = 0x02;		// ARP replay

			/*
			Send the packet to the (new) target hardware address on
	    	the same hardware on which the request was received.
			*/

			wrSer(' ');
			wrSer('r');
			wrSer('\n');

			startXmit(buf, 60);
		}

		wrSer('\n');
	}

	private static void swapAdr() {

		int i;

		for (i=0; i<6; ++i) {
			buf[0+i] = buf[6+i];	// old src->dest
			buf[32+i] = buf[6+i];	// arp dest addr
			buf[6+i] = eth[i];		// src
			buf[22+i] = eth[i];		// arp src addr
		}
		for (i=0; i<4; ++i) {		// set ip fields
			buf[38+i] = buf[28+i];
			buf[28+i] = ip[i];
		}
	}

	private static void ip() {

		wrSer('I');
	}

			

/*********************/

/**
*	'ISA Bus' io write cycle.
*/
	private static void wr(int data, int reg) {

		JopSys.wr(data, IO_ISA_DATA);					// data in buffer

		JopSys.wr(reg | ISA_DIR, IO_ISA_CTRL);			// addr and drive data out
		JopSys.wr(reg | ISA_WR | ISA_DIR, IO_ISA_CTRL);	// niow low
		JopSys.wr(reg | ISA_DIR, IO_ISA_CTRL);			// niow high again
		JopSys.wr(reg, IO_ISA_CTRL);					// disable dout
	}

/**
*	'ISA Bus' io read cycle.
*/
	private static int rd(int reg) {

		JopSys.wr(reg, IO_ISA_CTRL);					// addr
		JopSys.wr(reg | ISA_RD, IO_ISA_CTRL);			// nior low
		int ret = JopSys.rd(IO_ISA_DATA);				// read data
		JopSys.wr(reg, IO_ISA_CTRL);					// nior high again

		return ret;
	}

/**
*	DMA read from card memory.
*/
	private static void rdMem(int addr, int[] buf, int cnt) {

		int i;

		/* We should already be in page 0, but to be safe... */
		wr(E8390_PAGE0+E8390_START+E8390_NODMA, E8390_CMD);

		wr(cnt & 0xff, EN0_RCNTLO);
		wr(cnt >>> 8,  EN0_RCNTHI);
		wr(addr & 0xff, EN0_RSARLO);	/* DMA start */
		wr(addr >>> 8, EN0_RSARHI);
		wr(E8390_RREAD+E8390_START, E8390_CMD);