tb_fpu.vhd

来自「Java Op Processor java vhdl processor」· VHDL 代码 · 共 1,389 行 · 第 1/5 页

-------------------------------------------------------------------------------
--
-- Project:	<Floating Point Unit Core>
--  	
-- Description: test bench for the FPU core
-------------------------------------------------------------------------------
--
--				100101011010011100100
--				110000111011100100000
--				100000111011000101101
--				100010111100101111001
--				110000111011101101001
--				010000001011101001010
--				110100111001001100001
--				110111010000001100111
--				110110111110001011101
--				101110110010111101000
--				100000010111000000000
--
-- 	Author:		 Jidan Al-eryani 
-- 	E-mail: 	 [e-mail]
--
--  Copyright (C) 2006
--
--	This source file may be used and distributed without        
--	restriction provided that this copyright statement is not   
--	removed from the file and that any derivative work contains 
--	the original copyright notice and the associated disclaimer.
--                                                           
--		THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     
--	EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   
--	TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   
--	FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      
--	OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         
--	INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    
--	(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   
--	GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        
--	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  
--	LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  
--	(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  
--	OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         
--	POSSIBILITY OF SUCH DAMAGE. 
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;




entity tb_fpu is
end tb_fpu;

architecture rtl of tb_fpu is

component fpu 
    port (
        clk_i       	: in std_logic;
        opa_i       	: in std_logic_vector(31 downto 0);   
        opb_i       	: in std_logic_vector(31 downto 0);
        fpu_op_i		: in std_logic_vector(2 downto 0);
        rmode_i 		: in std_logic_vector(1 downto 0);  
        output_o    	: out std_logic_vector(31 downto 0);
		ine_o 			: out std_logic;
        overflow_o  	: out std_logic;
        underflow_o 	: out std_logic;
        div_zero_o  	: out std_logic;
        inf_o			: out std_logic;
        zero_o			: out std_logic;
        qnan_o			: out std_logic;
        snan_o			: out std_logic;
        start_i	  		: in  std_logic;
        ready_o 		: out std_logic	
	);   
end component;

component fpu_y
   port( 
      clk         : in     std_logic  ;
      fpu_op      : in     std_logic_vector (2 downto 0) ;
      opa         : in     std_logic_vector (31 downto 0) ;
      opb         : in     std_logic_vector (31 downto 0) ;
      rmode       : in     std_logic_vector (1 downto 0) ;
      div_by_zero : out    std_logic  ;
      fpout       : out    std_logic_vector (31 downto 0) ;
      ine         : out    std_logic  ;
      inf         : out    std_logic  ;
      overflow    : out    std_logic  ;
      qnan        : out    std_logic  ;
      snan        : out    std_logic  ;
      underflow   : out    std_logic  ;
      zero        : out    std_logic
      );
end component;

signal clk_i : std_logic:= '0';
signal opa_i, opb_i : std_logic_vector(31 downto 0);
signal fpu_op_i		: std_logic_vector(2 downto 0);
signal rmode_i : std_logic_vector(1 downto 0);
signal output_o : std_logic_vector(31 downto 0);
signal start_i, ready_o : std_logic ; 
signal ine_o, overflow_o, underflow_o, div_zero_o, inf_o, zero_o, qnan_o, snan_o: std_logic;

signal fpout_y : std_logic_vector (31 downto 0) ;
signal ine_y, inf_y, overflow_y, qnan_y, snan_y, underflow_y, zero_y, div_by_zero_y : std_logic ;

constant CLK_PERIOD :time := 10 ns; -- period of clk period

begin


    -- instantiate the fpu
    i_fpu: fpu port map (
			clk_i => clk_i,
			opa_i => opa_i,
			opb_i => opb_i,
			fpu_op_i =>	fpu_op_i,
			rmode_i => rmode_i,	
			output_o => output_o,  
			ine_o => ine_o,
			overflow_o => overflow_o,
			underflow_o => underflow_o,		
        	div_zero_o => div_zero_o,
        	inf_o => inf_o,
        	zero_o => zero_o,		
        	qnan_o => qnan_o, 		
        	snan_o => snan_o,
        	start_i => start_i,
        	ready_o => ready_o);		
			
		
		-- instantiate the fpu
    i_fpu_y: fpu_y port map (
        clk => clk_i,
        fpu_op => fpu_op_i,
        opa => opa_i,
        opb => opb_i,         
        rmode => rmode_i,     
        div_by_zero => div_by_zero_y, 
        fpout => fpout_y,       
        ine => ine_y,          
        inf => inf_y,         
        overflow => overflow_y,   
        qnan => qnan_y,        
        snan => snan_y,       
        underflow => underflow_y,  
        zero => zero_y);	


    ---------------------------------------------------------------------------
    -- toggle clock
    ---------------------------------------------------------------------------
    clk_i <= not(clk_i) after 5 ns;


    verify : process  
    begin
    
--************* Add/Substract Test Vectors****************
    	--			  seeeeeeeefffffffffffffffffffffff
    	wait for CLK_PERIOD; start_i <= '1'; opa_i <= "00000000100000000000000000000000"; 
			opb_i <= "00000000100000000000000000000000"; 
			fpu_op_i <= "000";
			rmode_i <= "00";
			wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
			assert output_o=fpout_y and ine_o=ine_y and overflow_o=overflow_y and underflow_o=underflow_y and inf_o=inf_y and zero_y=zero_o and div_zero_o=div_by_zero_y and qnan_o=qnan_y and snan_o=snan_y
			report "Error!!!"
			severity failure;

    	--			  seeeeeeeefffffffffffffffffffffff
    	wait for CLK_PERIOD; start_i <= '1'; opa_i <= "00000000110000000000000000000010"; 
			opb_i <= "00000000100000000000000000000000"; 
			fpu_op_i <= "000";
			rmode_i <= "00";
			wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
			assert output_o=fpout_y and ine_o=ine_y and overflow_o=overflow_y and underflow_o=underflow_y and inf_o=inf_y and zero_y=zero_o and div_zero_o=div_by_zero_y and qnan_o=qnan_y and snan_o=snan_y
			report "Error!!!"
			severity failure;
			
    	--			  seeeeeeeefffffffffffffffffffffff
    	wait for CLK_PERIOD; start_i <= '1'; opa_i <= "10000000000000000000000000000111"; 
			opb_i <= "10000000001111111111111111111000"; 
			fpu_op_i <= "000";
			rmode_i <= "00";
			wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
			assert output_o=fpout_y and ine_o=ine_y and overflow_o=overflow_y and underflow_o=underflow_y and inf_o=inf_y and zero_y=zero_o and div_zero_o=div_by_zero_y and qnan_o=qnan_y and snan_o=snan_y
			report "Error!!!"
			severity failure;

    	--			  seeeeeeeefffffffffffffffffffffff
    	wait for CLK_PERIOD; start_i <= '1'; opa_i <= "00000011111110100011111000101000"; 
			opb_i <= "00000111000101111000001111100110"; 
			fpu_op_i <= "000";
			rmode_i <= "00";
			wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
			assert output_o=fpout_y and ine_o=ine_y and overflow_o=overflow_y and underflow_o=underflow_y and inf_o=inf_y and zero_y=zero_o and div_zero_o=div_by_zero_y and qnan_o=qnan_y and snan_o=snan_y
			report "Error!!!"
			severity failure;		
			
    	--			  seeeeeeeefffffffffffffffffffffff
    	wait for CLK_PERIOD; start_i <= '1'; opa_i <= "10001100111110100011111000101000"; 
			opb_i <= "10001100111101111000001111100110"; 
			fpu_op_i <= "000";
			rmode_i <= "00";
			wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
			assert output_o=fpout_y and ine_o=ine_y and overflow_o=overflow_y and underflow_o=underflow_y and inf_o=inf_y and zero_y=zero_o and div_zero_o=div_by_zero_y and qnan_o=qnan_y and snan_o=snan_y
			report "Error!!!"
			severity failure;		

    	--			  seeeeeeeefffffffffffffffffffffff
    	wait for CLK_PERIOD; start_i <= '1'; opa_i <= "00000011111110100011111000101000"; 
			opb_i <= "01111111110000000000000000000001"; 
			fpu_op_i <= "000";
			rmode_i <= "00";
			wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
			assert output_o=fpout_y and ine_o=ine_y and overflow_o=overflow_y and underflow_o=underflow_y and inf_o=inf_y and zero_y=zero_o and div_zero_o=div_by_zero_y and qnan_o=qnan_y and snan_o=snan_y
			report "Error!!!"
			severity failure;
			
			--			  seeeeeeeefffffffffffffffffffffff
    	wait for CLK_PERIOD; start_i <= '1'; opa_i <= "00000011111110100011111000101000"; 
			opb_i <= "01111111100000000000000000000001"; 
			fpu_op_i <= "000";
			rmode_i <= "00";
			wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
			assert output_o=fpout_y and ine_o=ine_y and overflow_o=overflow_y and underflow_o=underflow_y and inf_o=inf_y and zero_y=zero_o and div_zero_o=div_by_zero_y and qnan_o=qnan_y and snan_o=snan_y
			report "Error!!!"
			severity failure;
			
			--			  seeeeeeeefffffffffffffffffffffff
    	wait for CLK_PERIOD; start_i <= '1'; opa_i <= "00000000100100000000000000000010"; 
			opb_i <= "00000000100000000000000000000000"; 
			fpu_op_i <= "000";
			rmode_i <= "00";
			wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
			assert output_o=fpout_y and ine_o=ine_y and overflow_o=overflow_y and underflow_o=underflow_y and inf_o=inf_y and zero_y=zero_o and div_zero_o=div_by_zero_y and qnan_o=qnan_y and snan_o=snan_y
			report "Error!!!"
			severity failure;
			
			--			  seeeeeeeefffffffffffffffffffffff
    	wait for CLK_PERIOD; start_i <= '1'; opa_i <= "00100011001000000000000000000000"; 
			opb_i <= "00101001100100000000000000000100"; 
			fpu_op_i <= "000";
			rmode_i <= "00";
			wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
			assert output_o=fpout_y and ine_o=ine_y and overflow_o=overflow_y and underflow_o=underflow_y and inf_o=inf_y and zero_y=zero_o and div_zero_o=div_by_zero_y and qnan_o=qnan_y and snan_o=snan_y
			report "Error!!!"
			severity failure;
			
			--			  seeeeeeeefffffffffffffffffffffff
    	wait for CLK_PERIOD; start_i <= '1'; opa_i <= "01110011011100000000000000000011"; 
			opb_i <= "01101100100000000000000000000000"; 
			fpu_op_i <= "000";
			rmode_i <= "00";
			wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
			assert output_o=fpout_y and ine_o=ine_y and overflow_o=overflow_y and underflow_o=underflow_y and inf_o=inf_y and zero_y=zero_o and div_zero_o=div_by_zero_y and qnan_o=qnan_y and snan_o=snan_y
			report "Error!!!"
			severity failure;
			
			--			  seeeeeeeefffffffffffffffffffffff
    	wait for CLK_PERIOD; start_i <= '1'; opa_i <= "00000000000000011111111111111111"; 
			opb_i <= "00000000000000000000000000111111"; 
			fpu_op_i <= "000";
			rmode_i <= "00";
			wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
			assert output_o=fpout_y and ine_o=ine_y and overflow_o=overflow_y and underflow_o=underflow_y and inf_o=inf_y and zero_y=zero_o and div_zero_o=div_by_zero_y and qnan_o=qnan_y and snan_o=snan_y
			report "Error!!!"
			severity failure;
			
			--			  seeeeeeeefffffffffffffffffffffff
    	wait for CLK_PERIOD; start_i <= '1'; opa_i <= "00000111111111111111111111111111"; 
			opb_i <= "00000000000001000000000000000000"; 
			fpu_op_i <= "000";
			rmode_i <= "00";