9729.v

汉字点阵源码 汉字点阵源码 汉字点阵源码

/*
module 9729(data_38,data_9729,clk_9729,load);
output [3:0]data_238;
output data_9729;
end module
*/
/*
module	zz_H ( CLK_40MHz, ROW, COLUMN );
   input   CLK_40MHz;
   output  [15:0] ROW, COLUMN;
   wire    CLK_1KHz;
	
   CNT  CNT (CLK_40MHz, CLK_1KHz);  
   9729 9729 ( CLK_1KHz, ROW, COLUMN );

endmodule
*/
/* 256点阵显示模块 */
module	9729 ( CLK, ROW, COLUMN );
   input   CLK;
   output  [15:0] ROW, COLUMN;
   reg     [15:0] ROW, COLUMN;		
   reg     [3:0] Q;

   initial
      begin
        COLUMN=16'b1111_1111_1111_1111;            
        ROW=16'b1111_1111_1111_1111;                
        Q=0;       
     end      

  always @(posedge CLK)        
     begin
       if (Q==15)
          Q=0;
       else
          Q=Q+1;
     end

   always @(posedge CLK)          
     begin 
        case (Q)
          4'b0000:begin  COLUMN=16'b1111_1111_1111_1110; ROW=16'b0000_0000_0000_1110; end   //1
          4'b0001:begin COLUMN=16'b1111_1111_1111_1101; ROW=16'b0000_0000_0000_0001;  end   //2
	  4'b0010:begin   COLUMN=16'b1111_1111_1111_1011; ROW=16'b0000_0000_0000_0001;end   //3
	  4'b0011:begin  COLUMN=16'b1111_1111_1111_0111;ROW=16'b0000_0000_0000_1110;  end   //4 

	  4'b0100:begin  ROW=16'b0000_0000_0001_0000; COLUMN=16'b1111_1111_1110_1111; end   //5
	  4'b0101:begin  ROW=16'b0000_0000_0001_0000; COLUMN=16'b1111_1111_1101_1111; end   //6
	  4'b0110:begin  ROW=16'b0000_0000_0000_1110; COLUMN=16'b1111_1111_1011_1111; end   //7
	  4'b0111:begin  ROW=16'b0000_0000_0000_0000; COLUMN=16'b1111_1111_0111_1111; end   //8

          4'b1000:begin  ROW=16'b0000_0000_0000_0000; COLUMN=16'b1111_1110_1111_1111; end   //9
          4'b1001:begin  ROW=16'b0000_0000_0000_0000; COLUMN=16'b1111_1101_1111_1111; end   //10
	  4'b1010:begin  ROW=16'b0000_0000_0000_0000; COLUMN=16'b1111_1011_1111_1111; end   //11
	  4'b1011:begin  ROW=16'b0000_0000_0000_0000; COLUMN=16'b1111_0111_1111_1111; end   //12

	  4'b1100:begin  ROW=16'b0000_0000_0000_0000; COLUMN=16'b1110_1111_1111_1111; end   //13	
	  4'b1101:begin  ROW=16'b0000_0000_0000_0000; COLUMN=16'b1110_1111_1111_1111; end   //14	
	  4'b1110:begin  ROW=16'b0000_0000_0000_0000; COLUMN=16'b1011_1111_1111_1111; end   //15	
	  4'b1111:begin  ROW=16'b0000_0000_0000_0000; COLUMN=16'b0111_1111_1111_1111; end   //16
       endcase  
    end 

endmodule

/**********分频模块 ***********/
module	CNT (CLK, DIV_CLK);  
    input	CLK;           
    reg 	[15:0] Q;   
    output	DIV_CLK;          
  
    always @(posedge CLK)       
      begin   
        if (Q==39999)                
            Q<=0;                  
         else 
            Q<=Q+1;    
      end           

    assign  DIV_CLK=~Q[15];        
endmodule