rgb.tan.qmsg

汉字显示屏 汉字显示屏 汉字显示屏

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register Q\[0\] COLUMN\[11\]~reg0 275.03 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 275.03 MHz between source register \"Q\[0\]\" and destination register \"COLUMN\[11\]~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.690 ns + Longest register register " "Info: + Longest register to register delay is 1.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q\[0\] 1 REG LC_X22_Y15_N3 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y15_N3; Fanout = 20; REG Node = 'Q\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Q[0] } "NODE_NAME" } } { "rgb.v" "" { Text "C:/Documents and Settings/Administrator/桌面/rgb/rgb.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.952 ns) + CELL(0.738 ns) 1.690 ns COLUMN\[11\]~reg0 2 REG LC_X23_Y15_N5 1 " "Info: 2: + IC(0.952 ns) + CELL(0.738 ns) = 1.690 ns; Loc. = LC_X23_Y15_N5; Fanout = 1; REG Node = 'COLUMN\[11\]~reg0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.690 ns" { Q[0] COLUMN[11]~reg0 } "NODE_NAME" } } { "rgb.v" "" { Text "C:/Documents and Settings/Administrator/桌面/rgb/rgb.v" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 43.67 % ) " "Info: Total cell delay = 0.738 ns ( 43.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.952 ns ( 56.33 % ) " "Info: Total interconnect delay = 0.952 ns ( 56.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.690 ns" { Q[0] COLUMN[11]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.690 ns" { Q[0] COLUMN[11]~reg0 } { 0.000ns 0.952ns } { 0.000ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'CLK'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "rgb.v" "" { Text "C:/Documents and Settings/Administrator/桌面/rgb/rgb.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns COLUMN\[11\]~reg0 2 REG LC_X23_Y15_N5 1 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X23_Y15_N5; Fanout = 1; REG Node = 'COLUMN\[11\]~reg0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { CLK COLUMN[11]~reg0 } "NODE_NAME" } } { "rgb.v" "" { Text "C:/Documents and Settings/Administrator/桌面/rgb/rgb.v" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { CLK COLUMN[11]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 COLUMN[11]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.962 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'CLK'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "rgb.v" "" { Text "C:/Documents and Settings/Administrator/桌面/rgb/rgb.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns Q\[0\] 2 REG LC_X22_Y15_N3 20 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X22_Y15_N3; Fanout = 20; REG Node = 'Q\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { CLK Q[0] } "NODE_NAME" } } { "rgb.v" "" { Text "C:/Documents and Settings/Administrator/桌面/rgb/rgb.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { CLK Q[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 Q[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { CLK COLUMN[11]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 COLUMN[11]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { CLK Q[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 Q[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "rgb.v" "" { Text "C:/Documents and Settings/Administrator/桌面/rgb/rgb.v" 38 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "rgb.v" "" { Text "C:/Documents and Settings/Administrator/桌面/rgb/rgb.v" 63 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.690 ns" { Q[0] COLUMN[11]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.690 ns" { Q[0] COLUMN[11]~reg0 } { 0.000ns 0.952ns } { 0.000ns 0.738ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { CLK COLUMN[11]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 COLUMN[11]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { CLK Q[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 Q[0] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { COLUMN[11]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { COLUMN[11]~reg0 } {  } {  } } } { "rgb.v" "" { Text "C:/Documents and Settings/Administrator/桌面/rgb/rgb.v" 63 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK ROW\[2\] ROW\[3\]~reg0 9.157 ns register " "Info: tco from clock \"CLK\" to destination pin \"ROW\[2\]\" through register \"ROW\[3\]~reg0\" is 9.157 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.962 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'CLK'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "rgb.v" "" { Text "C:/Documents and Settings/Administrator/桌面/rgb/rgb.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns ROW\[3\]~reg0 2 REG LC_X22_Y15_N5 3 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X22_Y15_N5; Fanout = 3; REG Node = 'ROW\[3\]~reg0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { CLK ROW[3]~reg0 } "NODE_NAME" } } { "rgb.v" "" { Text "C:/Documents and Settings/Administrator/桌面/rgb/rgb.v" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { CLK ROW[3]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 ROW[3]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "rgb.v" "" { Text "C:/Documents and Settings/Administrator/桌面/rgb/rgb.v" 63 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.971 ns + Longest register pin " "Info: + Longest register to pin delay is 5.971 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ROW\[3\]~reg0 1 REG LC_X22_Y15_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y15_N5; Fanout = 3; REG Node = 'ROW\[3\]~reg0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ROW[3]~reg0 } "NODE_NAME" } } { "rgb.v" "" { Text "C:/Documents and Settings/Administrator/桌面/rgb/rgb.v" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.847 ns) + CELL(2.124 ns) 5.971 ns ROW\[2\] 2 PIN PIN_21 0 " "Info: 2: + IC(3.847 ns) + CELL(2.124 ns) = 5.971 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'ROW\[2\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.971 ns" { ROW[3]~reg0 ROW[2] } "NODE_NAME" } } { "rgb.v" "" { Text "C:/Documents and Settings/Administrator/桌面/rgb/rgb.v" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 35.57 % ) " "Info: Total cell delay = 2.124 ns ( 35.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.847 ns ( 64.43 % ) " "Info: Total interconnect delay = 3.847 ns ( 64.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.971 ns" { ROW[3]~reg0 ROW[2] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.971 ns" { ROW[3]~reg0 ROW[2] } { 0.000ns 3.847ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { CLK ROW[3]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { CLK CLK~out0 ROW[3]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.971 ns" { ROW[3]~reg0 ROW[2] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.971 ns" { ROW[3]~reg0 ROW[2] } { 0.000ns 3.847ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 21 13:33:02 2007 " "Info: Processing ended: Sat Apr 21 13:33:02 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}