⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 rgb.fit.rpt

📁 汉字显示屏 汉字显示屏 汉字显示屏
💻 RPT
字号:
Fitter report for rgb
Tue Apr 24 16:58:38 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Failed - Tue Apr 24 16:58:38 2007        ;
; Quartus II Version    ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name         ; rgb                                      ;
; Top-level Entity Name ; rgb                                      ;
; Family                ; Cyclone                                  ;
; Device                ; EP1C6Q240C8                              ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 22                                       ;
; Total pins            ; 33                                       ;
; Total virtual pins    ; 0                                        ;
; Total memory bits     ; 0                                        ;
; Total PLLs            ; 0                                        ;
+-----------------------+------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                      ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option                                             ; Setting                        ; Default Value                  ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device                                             ; EP1C6Q240C8                    ;                                ;
; Use smart compilation                              ; Off                            ; Off                            ;
; Router Timing Optimization Level                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                        ; Off                            ; Off                            ;
; Optimize Timing                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing         ; On                             ; On                             ;
; Limit to One Fitting Attempt                       ; Off                            ; Off                            ;
; Final Placement Optimizations                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                      ; 1                              ; 1                              ;
; Slow Slew Rate                                     ; Off                            ; Off                            ;
; PCI I/O                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                  ; On                             ; On                             ;
; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;
; Perform Register Duplication                       ; Off                            ; Off                            ;
; Perform Register Retiming                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining             ; Off                            ; Off                            ;
; Fitter Effort                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication           ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+---------------------------------------------------------------+
; Fitter Device Options                                         ;
+----------------------------------------------+----------------+
; Option                                       ; Setting        ;
+----------------------------------------------+----------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off            ;
; Enable device-wide reset (DEV_CLRn)          ; Off            ;
; Enable device-wide output enable (DEV_OE)    ; Off            ;
; Enable INIT_DONE output                      ; Off            ;
; Configuration scheme                         ; Passive Serial ;
; Error detection CRC                          ; Off            ;
; Base pin-out file on sameframe device        ; Off            ;
+----------------------------------------------+----------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 24 16:58:38 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off rgb -c rgb
Warning: FLEXlm software error: Invalid (inconsistent) license key  The license-key and data for the feature do not match.  This usually happens when a license file has been altered Feature:       quartus_lite License path:  I:\FPGA\001617C07577__0-259375660335354.dat FLEXlm error:  -8,523 For further information, refer to the FLEXlm End User Manual, available at "www.macrovision.com".
Error: Current license file does not support the EP1C6Q240C8 device
Error: Quartus II Fitter was unsuccessful. 1 error, 1 warning
    Error: Processing ended: Tue Apr 24 16:58:38 2007
    Error: Elapsed time: 00:00:00


⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -