📄 rgb.tan.rpt
字号:
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[10]~reg0 ; CLK ; CLK ; None ; None ; 1.463 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[14]~reg0 ; CLK ; CLK ; None ; None ; 1.463 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[6]~reg0 ; CLK ; CLK ; None ; None ; 1.461 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[8]~reg0 ; CLK ; CLK ; None ; None ; 1.459 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[5]~reg0 ; CLK ; CLK ; None ; None ; 1.457 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[9]~reg0 ; CLK ; CLK ; None ; None ; 1.454 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; ROW[4]~reg0 ; CLK ; CLK ; None ; None ; 1.449 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[4]~reg0 ; CLK ; CLK ; None ; None ; 1.446 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[7]~reg0 ; CLK ; CLK ; None ; None ; 1.441 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[12]~reg0 ; CLK ; CLK ; None ; None ; 1.364 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[15]~reg0 ; CLK ; CLK ; None ; None ; 1.362 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; Q[3] ; CLK ; CLK ; None ; None ; 1.341 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; ROW[4]~reg0 ; CLK ; CLK ; None ; None ; 1.269 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; ROW[3]~reg0 ; CLK ; CLK ; None ; None ; 1.265 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[0]~reg0 ; CLK ; CLK ; None ; None ; 1.265 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; ROW[0]~reg0 ; CLK ; CLK ; None ; None ; 1.264 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; Q[2] ; CLK ; CLK ; None ; None ; 1.263 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[3]~reg0 ; CLK ; CLK ; None ; None ; 1.261 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[12]~reg0 ; CLK ; CLK ; None ; None ; 1.260 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[15]~reg0 ; CLK ; CLK ; None ; None ; 1.260 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[1]~reg0 ; CLK ; CLK ; None ; None ; 1.259 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[2]~reg0 ; CLK ; CLK ; None ; None ; 1.259 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; ROW[3]~reg0 ; CLK ; CLK ; None ; None ; 1.216 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[0]~reg0 ; CLK ; CLK ; None ; None ; 1.215 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; ROW[0]~reg0 ; CLK ; CLK ; None ; None ; 1.214 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[1]~reg0 ; CLK ; CLK ; None ; None ; 1.214 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[2]~reg0 ; CLK ; CLK ; None ; None ; 1.212 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[3]~reg0 ; CLK ; CLK ; None ; None ; 1.211 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; Q[3] ; CLK ; CLK ; None ; None ; 1.202 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; Q[1] ; CLK ; CLK ; None ; None ; 1.195 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; ROW[3]~reg0 ; CLK ; CLK ; None ; None ; 1.093 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[0]~reg0 ; CLK ; CLK ; None ; None ; 1.092 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[15]~reg0 ; CLK ; CLK ; None ; None ; 1.092 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[12]~reg0 ; CLK ; CLK ; None ; None ; 1.091 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; ROW[0]~reg0 ; CLK ; CLK ; None ; None ; 1.089 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[3]~reg0 ; CLK ; CLK ; None ; None ; 1.089 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[2]~reg0 ; CLK ; CLK ; None ; None ; 1.087 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[1]~reg0 ; CLK ; CLK ; None ; None ; 1.083 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; Q[2] ; CLK ; CLK ; None ; None ; 1.029 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; Q[3] ; CLK ; CLK ; None ; None ; 1.029 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; Q[1] ; CLK ; CLK ; None ; None ; 0.981 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; Q[3] ; CLK ; CLK ; None ; None ; 0.980 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; Q[0] ; CLK ; CLK ; None ; None ; 0.978 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; Q[2] ; CLK ; CLK ; None ; None ; 0.932 ns ;
+-------+------------------------------------------------+------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-----------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-----------------+------------+------------+
; N/A ; None ; 9.157 ns ; ROW[3]~reg0 ; ROW[2] ; CLK ;
; N/A ; None ; 9.157 ns ; ROW[3]~reg0 ; ROW[1] ; CLK ;
; N/A ; None ; 8.523 ns ; ROW[3]~reg0 ; ROW[3] ; CLK ;
; N/A ; None ; 8.480 ns ; ROW[0]~reg0 ; ROW[0] ; CLK ;
; N/A ; None ; 8.389 ns ; COLUMN[14]~reg0 ; COLUMN[14] ; CLK ;
; N/A ; None ; 7.992 ns ; COLUMN[1]~reg0 ; COLUMN[1] ; CLK ;
; N/A ; None ; 7.869 ns ; COLUMN[2]~reg0 ; COLUMN[2] ; CLK ;
; N/A ; None ; 7.835 ns ; COLUMN[9]~reg0 ; COLUMN[9] ; CLK ;
; N/A ; None ; 7.834 ns ; COLUMN[7]~reg0 ; COLUMN[7] ; CLK ;
; N/A ; None ; 7.685 ns ; COLUMN[0]~reg0 ; COLUMN[0] ; CLK ;
; N/A ; None ; 7.548 ns ; COLUMN[12]~reg0 ; COLUMN[12] ; CLK ;
; N/A ; None ; 7.414 ns ; COLUMN[11]~reg0 ; COLUMN[11] ; CLK ;
; N/A ; None ; 7.414 ns ; COLUMN[5]~reg0 ; COLUMN[5] ; CLK ;
; N/A ; None ; 7.377 ns ; COLUMN[4]~reg0 ; COLUMN[4] ; CLK ;
; N/A ; None ; 7.081 ns ; COLUMN[8]~reg0 ; COLUMN[8] ; CLK ;
; N/A ; None ; 7.079 ns ; COLUMN[6]~reg0 ; COLUMN[6] ; CLK ;
; N/A ; None ; 7.068 ns ; COLUMN[15]~reg0 ; COLUMN[15] ; CLK ;
; N/A ; None ; 7.068 ns ; COLUMN[10]~reg0 ; COLUMN[10] ; CLK ;
; N/A ; None ; 7.068 ns ; COLUMN[3]~reg0 ; COLUMN[3] ; CLK ;
; N/A ; None ; 7.068 ns ; ROW[4]~reg0 ; ROW[4] ; CLK ;
+-------+--------------+------------+-----------------+------------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sat Apr 21 13:33:01 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off rgb -c rgb --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 275.03 MHz between source register "Q[0]" and destination register "COLUMN[11]~reg0"
Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.690 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y15_N3; Fanout = 20; REG Node = 'Q[0]'
Info: 2: + IC(0.952 ns) + CELL(0.738 ns) = 1.690 ns; Loc. = LC_X23_Y15_N5; Fanout = 1; REG Node = 'COLUMN[11]~reg0'
Info: Total cell delay = 0.738 ns ( 43.67 % )
Info: Total interconnect delay = 0.952 ns ( 56.33 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "CLK" to destination register is 2.962 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'CLK'
Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X23_Y15_N5; Fanout = 1; REG Node = 'COLUMN[11]~reg0'
Info: Total cell delay = 2.180 ns ( 73.60 % )
Info: Total interconnect delay = 0.782 ns ( 26.40 % )
Info: - Longest clock path from clock "CLK" to source register is 2.962 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'CLK'
Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X22_Y15_N3; Fanout = 20; REG Node = 'Q[0]'
Info: Total cell delay = 2.180 ns ( 73.60 % )
Info: Total interconnect delay = 0.782 ns ( 26.40 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "CLK" to destination pin "ROW[2]" through register "ROW[3]~reg0" is 9.157 ns
Info: + Longest clock path from clock "CLK" to source register is 2.962 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'CLK'
Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X22_Y15_N5; Fanout = 3; REG Node = 'ROW[3]~reg0'
Info: Total cell delay = 2.180 ns ( 73.60 % )
Info: Total interconnect delay = 0.782 ns ( 26.40 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 5.971 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y15_N5; Fanout = 3; REG Node = 'ROW[3]~reg0'
Info: 2: + IC(3.847 ns) + CELL(2.124 ns) = 5.971 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'ROW[2]'
Info: Total cell delay = 2.124 ns ( 35.57 % )
Info: Total interconnect delay = 3.847 ns ( 64.43 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Sat Apr 21 13:33:02 2007
Info: Elapsed time: 00:00:01
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