📄 rgb.tan.rpt
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Timing Analyzer report for rgb
Sat Apr 21 13:33:02 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'CLK'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+-------------+-----------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-------------+-----------------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 9.157 ns ; ROW[3]~reg0 ; ROW[1] ; CLK ; -- ; 0 ;
; Clock Setup: 'CLK' ; N/A ; None ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[11]~reg0 ; CLK ; CLK ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+-------------+-----------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK' ;
+-------+------------------------------------------------+------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[11]~reg0 ; CLK ; CLK ; None ; None ; 1.690 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[10]~reg0 ; CLK ; CLK ; None ; None ; 1.689 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[14]~reg0 ; CLK ; CLK ; None ; None ; 1.688 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[6]~reg0 ; CLK ; CLK ; None ; None ; 1.687 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[7]~reg0 ; CLK ; CLK ; None ; None ; 1.687 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[4]~reg0 ; CLK ; CLK ; None ; None ; 1.686 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[8]~reg0 ; CLK ; CLK ; None ; None ; 1.685 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[9]~reg0 ; CLK ; CLK ; None ; None ; 1.685 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[5]~reg0 ; CLK ; CLK ; None ; None ; 1.683 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[7]~reg0 ; CLK ; CLK ; None ; None ; 1.667 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[4]~reg0 ; CLK ; CLK ; None ; None ; 1.666 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[9]~reg0 ; CLK ; CLK ; None ; None ; 1.664 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[5]~reg0 ; CLK ; CLK ; None ; None ; 1.662 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[8]~reg0 ; CLK ; CLK ; None ; None ; 1.660 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[6]~reg0 ; CLK ; CLK ; None ; None ; 1.658 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[11]~reg0 ; CLK ; CLK ; None ; None ; 1.656 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[10]~reg0 ; CLK ; CLK ; None ; None ; 1.655 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; COLUMN[14]~reg0 ; CLK ; CLK ; None ; None ; 1.654 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; ROW[3]~reg0 ; CLK ; CLK ; None ; None ; 1.630 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[0]~reg0 ; CLK ; CLK ; None ; None ; 1.630 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; ROW[0]~reg0 ; CLK ; CLK ; None ; None ; 1.629 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[3]~reg0 ; CLK ; CLK ; None ; None ; 1.626 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[2]~reg0 ; CLK ; CLK ; None ; None ; 1.624 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[1]~reg0 ; CLK ; CLK ; None ; None ; 1.616 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[11]~reg0 ; CLK ; CLK ; None ; None ; 1.565 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[10]~reg0 ; CLK ; CLK ; None ; None ; 1.564 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[14]~reg0 ; CLK ; CLK ; None ; None ; 1.563 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[6]~reg0 ; CLK ; CLK ; None ; None ; 1.561 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[8]~reg0 ; CLK ; CLK ; None ; None ; 1.559 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[5]~reg0 ; CLK ; CLK ; None ; None ; 1.557 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[9]~reg0 ; CLK ; CLK ; None ; None ; 1.554 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[4]~reg0 ; CLK ; CLK ; None ; None ; 1.549 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[3] ; COLUMN[7]~reg0 ; CLK ; CLK ; None ; None ; 1.549 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[2] ; ROW[4]~reg0 ; CLK ; CLK ; None ; None ; 1.491 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[0] ; COLUMN[15]~reg0 ; CLK ; CLK ; None ; None ; 1.483 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Q[1] ; COLUMN[11]~reg0 ; CLK ; CLK ; None ; None ; 1.464 ns ;
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