rgb.map.rpt

汉字显示屏 汉字显示屏 汉字显示屏

+----------------------------------+-----------------+------------------------+--------------------------------------------------------+
; rgb.v                            ; yes             ; User Verilog HDL File  ; C:/Documents and Settings/Administrator/桌面/rgb/rgb.v ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 22    ;
;     -- Combinational with no register       ; 0     ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 22    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 17    ;
;     -- 3 input functions                    ; 3     ;
;     -- 2 input functions                    ; 1     ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 22    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 22    ;
; I/O pins                                    ; 33    ;
; Maximum fan-out node                        ; CLK   ;
; Maximum fan-out                             ; 22    ;
; Total fan-out                               ; 122   ;
; Average fan-out                             ; 2.22  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |rgb                       ; 22 (22)     ; 22           ; 0           ; 0    ; 33   ; 0            ; 0 (0)        ; 0 (0)             ; 22 (22)          ; 0 (0)           ; 0 (0)      ; |rgb                ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 22    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 24 16:58:35 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rgb -c rgb
Info: Found 2 design units, including 2 entities, in source file rgb.v
    Info: Found entity 1: rgb
    Info: Found entity 2: CNT
Info: Elaborating entity "rgb" for the top level hierarchy
Warning (10101): Verilog HDL unsupported feature warning at rgb.v(72): Initial Construct is not supported and will be ignored
Warning (10230): Verilog HDL assignment warning at rgb.v(83): truncated value with size 32 to match size of target (4)
Info: Power-up level of register "COLUMN[13]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "COLUMN[13]~reg0" with stuck data_in port to stuck value VCC
Warning: Reduced register "ROW[15]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "ROW[14]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "ROW[13]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "ROW[12]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "ROW[11]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "ROW[10]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "ROW[9]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "ROW[8]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "ROW[7]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "ROW[6]~reg0" with stuck data_in port to stuck value GND
Warning: Reduced register "ROW[5]~reg0" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "ROW[2]~reg0" merged to single register "ROW[3]~reg0"
    Info: Duplicate register "ROW[1]~reg0" merged to single register "ROW[3]~reg0"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "ROW[5]" stuck at GND
    Warning: Pin "ROW[6]" stuck at GND
    Warning: Pin "ROW[7]" stuck at GND
    Warning: Pin "ROW[8]" stuck at GND
    Warning: Pin "ROW[9]" stuck at GND
    Warning: Pin "ROW[10]" stuck at GND
    Warning: Pin "ROW[11]" stuck at GND
    Warning: Pin "ROW[12]" stuck at GND
    Warning: Pin "ROW[13]" stuck at GND
    Warning: Pin "ROW[14]" stuck at GND
    Warning: Pin "ROW[15]" stuck at GND
    Warning: Pin "COLUMN[13]" stuck at VCC
Info: Implemented 55 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 32 output pins
    Info: Implemented 22 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 27 warnings
    Info: Processing ended: Tue Apr 24 16:58:36 2007
    Info: Elapsed time: 00:00:01