motor_synthesis.nlf

用于CPLD的控制

Release 8.1i - netgen I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -w -dir netgen/synthesis -ofmt verilog -sim
motor.ngc motor_synthesis.v  

Reading design 'motor.ngc' ...
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing Verilog netlist file
'F:\practice\PLD\motor\netgen\synthesis\motor_synthesis.v' ...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM
   simulation primitives and has to be used with UNISIM simulation library for
   correct compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 57504 kilobytes