at91rm92000_full.h

uC/OS-II在AT91RM9200上移植所要用到的硬件相关头文件

//==========================================================================
//
// at91rm9200.h
//
// Author(s):    Michael Kelly, Cogent Computer Systems, Inc.
// Contributors: Christian Legare, Micrium
// Date:         6/20/2006
// Description:  This file contains the AT91RM9200 register defines
//				 and access macros.  Note that some register offsets
//               and most bit defines are located in separate, function
//				 specific files.


#ifndef AT91RM9200_FULL_H
#define AT91RM9200_FULL_H

// *****************************************************************************
// Advanced Interrupt Controller
// *****************************************************************************

// Source Mode Register - 32 of them
#define AIC_SMR_BASE		0xFFFFF000
#define AIC_SMR_REG(_x_)	*(vulong *)(AIC_SMR_BASE + (_x_ & 0x7f))

// Source Vector Register - 32 of them
#define AIC_SVR_BASE		0xFFFFF080
#define AIC_SVR_REG(_x_)	*(vulong *)(AIC_SVR_BASE + (_x_ & 0x7f))

// Control Register - 32 of them
#define AIC_CTL_BASE		0xFFFFF100
#define AIC_CTL_REG(_x_)	*(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f))

/*
// Register Offsets
#define AIC_IVR 	0x00	// IRQ Vector Register
#define AIC_FVR 	0x04	// FIQ Vector Register
#define AIC_ISR 	0x08	// Interrupt Status Register
#define AIC_IPR 	0x0C	// Interrupt Pending Register
#define AIC_IMR 	0x10	// Interrupt Mask Register
#define AIC_CISR 	0x14	// Core Interrupt Status Register
#define AIC_IECR 	0x20	// Interrupt Enable Command Register
#define AIC_IDCR 	0x24	// Interrupt Disable Command Register
#define AIC_ICCR 	0x28	// Interrupt Clear Command Register
#define AIC_ISCR 	0x2C	// Interrupt Set Command Register
#define AIC_EOICR 	0x30	// End of Interrupt Command Register
#define AIC_SPU 	0x34	// Spurious Vector Register
#define AIC_DCR 	0x38	// Debug Control Register (Protect)
#define AIC_FFER 	0x40	// Fast Forcing Enable Register
#define AIC_FFDR 	0x44	// Fast Forcing Disable Register
#define AIC_FFSR 	0x48	// Fast Forcing Status Register
*/

// *****************************************************************************
// Debug Unit
// *****************************************************************************
#define DBGU_BASE		0xFFFFF200
#define DBGU_REG(_x_)	*(vulong *)(DBGU_BASE + _x_)

// Register Offsets
#define DBGU_CR 	0x00	// Control Register
#define DBGU_MR 	0x04	// Mode Register
#define DBGU_IER 	0x08	// Interrupt Enable Register
#define DBGU_IDR 	0x0C	// Interrupt Disable Register
#define DBGU_IMR 	0x10	// Interrupt Mask Register
#define DBGU_CSR 	0x14	// Channel Status Register
#define DBGU_RHR 	0x18	// Receiver Holding Register
#define DBGU_THR 	0x1C	// Transmitter Holding Register
#define DBGU_BRGR 	0x20	// Baud Rate Generator Register
#define DBGU_C1R 	0x40	// Chip ID1 Register
#define DBGU_C2R 	0x44	// Chip ID2 Register
#define DBGU_FNTR 	0x48	// Force NTRST Register

// *****************************************************************************
// Peripheral Data Control (DMA)
// Note that each of the following peripherals has it's own
// set of these registers starting at offset 0x100 from it's
// base address: DBGU, SPI, USART and SSC
// To access the DMA for a peripheral, use the macro for that
// peripheral but with these register offsets
// *****************************************************************************
/*
// Register Offsets
#define PDC_RPR 	0x100	// Receive Pointer Register
#define PDC_RCR 	0x104	// Receive Counter Register
#define PDC_TPR 	0x108	// Transmit Pointer Register
#define PDC_TCR 	0x10c	// Transmit Counter Register
#define PDC_RNPR 	0x110	// Receive Next Pointer Register
#define PDC_RNCR 	0x114	// Receive Next Counter Register
#define PDC_TNPR 	0x118	// Transmit Next Pointer Register
#define PDC_TNCR 	0x11c	// Transmit Next Counter Register
#define PDC_PTCR 	0x120	// PDC Transfer Control Register
#define PDC_PTSR 	0x124	// PDC Transfer Status Register
*/

// *****************************************************************************
// Parallel I/O Unit
// There are four PIO blocks - A, B, C and D.  They all have the
// same register set, but different base addresses
// *****************************************************************************
// Port A
#define PIOA_BASE		0xFFFFF400
#define PIOA_REG(_x_)	*(vulong *)(PIOA_BASE + _x_)

// Port B
#define PIOB_BASE		0xFFFFF600
#define PIOB_REG(_x_)	*(vulong *)(PIOB_BASE + _x_)

// Port C
#define PIOC_BASE		0xFFFFF800
#define PIOC_REG(_x_)	*(vulong *)(PIOC_BASE + _x_)

// Port D
#define PIOD_BASE		0xFFFFFA00
#define PIOD_REG(_x_)	*(vulong *)(PIOD_BASE + _x_)

// *****************************************************************************
// Power Management and Clock Control
// *****************************************************************************
#define PMC_BASE		0xFFFFFC00
#define PMC_REG(_x_)	*(vulong *)(PMC_BASE + _x_)

/*
// Register Offsets
#define PMC_SCER 	0x00	// System Clock Enable Register
#define PMC_SCDR 	0x04	// System Clock Disable Register
#define PMC_SCSR 	0x08	// System Clock Status Register
#define PMC_PCER 	0x10	// Peripheral Clock Enable Register
#define PMC_PCDR 	0x14	// Peripheral Clock Disable Register
#define PMC_PCSR 	0x18	// Peripheral Clock Status Register
#define PMC_MOR 	0x20	// Main Oscillator Register
#define PMC_MCFR 	0x24	// Main Clock  Frequency Register
#define PMC_PLLAR 	0x28	// PLL A Register
#define PMC_PLLBR 	0x2C	// PLL B Register
#define PMC_MCKR 	0x30	// Master Clock Register
#define PMC_PCKR0 	0x40	// Programmable Clock Register 0
#define PMC_PCKR1 	0x44	// Programmable Clock Register 1
#define PMC_PCKR2 	0x48	// Programmable Clock Register 2
#define PMC_PCKR3 	0x4C	// Programmable Clock Register 3
#define PMC_PCKR4 	0x50	// Programmable Clock Register 4
#define PMC_PCKR5 	0x54	// Programmable Clock Register 5
#define PMC_PCKR6 	0x58	// Programmable Clock Register 6
#define PMC_PCKR7 	0x5C	// Programmable Clock Register 7
#define PMC_IER 	0x60	// Interrupt Enable Register
#define PMC_IDR 	0x64	// Interrupt Disable Register
#define PMC_SR 		0x68	// Status Register
#define PMC_IMR 	0x6C	// Interrupt Mask Register

#define ST_CR 		0x00	// Control Register
#define ST_PIMR 	0x04	// Period Interval Mode Register
#define ST_WDMR 	0x08	// Watchdog Mode Register
#define ST_RTMR 	0x0C	// Real-time Mode Register
#define ST_SR 		0x10	// Status Register
#define ST_IER 		0x14	// Interrupt Enable Register
#define ST_IDR 		0x18	// Interrupt Disable Register
#define ST_IMR 		0x1C	// Interrupt Mask Register
#define ST_RTAR 	0x20	// Real-time Alarm Register
#define ST_CRTR 	0x24	// Current Real-time Register

#define RTC_CR 		0x00	// Control Register
#define RTC_MR 		0x04	// Mode Register
#define RTC_TIMR 	0x08	// Time Register
#define RTC_CALR 	0x0C	// Calendar Register
#define RTC_TIMALR 	0x10	// Time Alarm Register
#define RTC_CALALR 	0x14	// Calendar Alarm Register
#define RTC_SR 		0x18	// Status Register
#define RTC_SCCR 	0x1C	// Status Clear Command Register
#define RTC_IER 	0x20	// Interrupt Enable Register
#define RTC_IDR 	0x24	// Interrupt Disable Register
#define RTC_IMR 	0x28	// Interrupt Mask Register
#define RTC_VER 	0x2C	// Valid Entry Register

#define MC_RCR 		0x00	// MC Remap Control Register
#define MC_ASR 		0x04	// MC Abort Status Register
#define MC_AASR 	0x08	// MC Abort Address Status Register
#define MC_MPR  	0x0C	// MC Master Priority Register
*/

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
// *****************************************************************************
typedef struct _AT91S_MC {
	AT91_REG	 MC_RCR; 	// MC Remap Control Register
	AT91_REG	 MC_ASR; 	// MC Abort Status Register
	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
	AT91_REG	 MC_MPR; 	// MC Master Priority Register
} AT91S_MC, *AT91PS_MC;

// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------