bootloader_arm.i

Sharp LH75401(ARM7)处理器部分控制程序。

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 ; $Workfile:   bootloader_arm.i  $ 
 ; $Revision:   0.00  $ 
 ; $Author:     AnvikE  $ 
 ; $Date:       Mar 06 2003   $ 
 ; 
 ; Project:     LH754XX
 ; 
 ; Description: 
 ;  This file is a header file for KEV754XX chip boot code..
 ; 
 ; Revision History: 
 ; 				
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;  
 ; 
 ;  Copyright (c) 2002 Sharp Microelectronics of the Americas 
 ; 
 ;  All rights reserved 
 ; 
 ;  SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION 
 ;  OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE, 
 ;  AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 ;  SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE. 
 ; 
 ;  SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 ;  FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 ;  SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE 
 ;  FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS. 
 ; 				
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; LH75401 xPSR (Processor Status Rgeister) bits 
MODE_USR    EQU 0x010
MODE_FIQ    EQU 0x011
MODE_IRQ    EQU 0x012
MODE_SVC    EQU 0x013
MODE_ABORT  EQU 0x017
MODE_UNDEF  EQU 0x01b
MODE_SYSTEM EQU 0x01F
I_MASK      EQU 0x080
F_MASK      EQU 0x040
T_MASK      EQU 0x020

; External Static RAM on external data bus 
EXTERNAL_SRAM_BASE EQU 0x44000000
EXTERNAL_SRAM_SIZE EQU 0x00100000	; 1Mbyte 
EXTERNAL_SRAM_END  EQU EXTERNAL_SRAM_BASE + EXTERNAL_SRAM_SIZE

; Internal Ram on the H-bus (DMA accessible) 
INTERNAL_SRAM_BASE EQU 0x60000000
INTERNAL_SRAM_SIZE EQU 0x00004000	; 16Kbytes 
INTERNAL_SRAM_END  EQU INTERNAL_SRAM_BASE + INTERNAL_SRAM_SIZE

; TCM (tightly coupled) SRAM on the Arm core (Not DMA accessible) 
TCM_SRAM_BASE      EQU 0x80000000
TCM_SRAM_SIZE	   EQU 0x00004000	; 16Kbytes 
TCM_SRAM_END	   EQU TCM_SRAM_BASE + TCM_SRAM_SIZE

; Flash ROM 
EXTERNAL_FLASH_BASE EQU 0x40000000
EXTERNAL_FLASH_SIZE EQU 0x00400000	; 4Mbytes   
EXTERNAL_FLASH_END  EQU EXTERNAL_FLASH_BASE + EXTERNAL_FLASH_SIZE

; Stacks locations 
EXCEPTION_STACK     EQU TCM_SRAM_END - 4
C_STACK		    EQU EXTERNAL_SRAM_END - 4
    
; SMC (Static Memory Controller) registers 
SMC_REG_BASE       EQU 0xFFFF1000
SMC_BCR0_OFFSET    EQU 0x00
SMC_BCR1_OFFSET	   EQU 0x04
SMC_BCR2_OFFSET	   EQU 0x08
SMC_BCR0_INIT      EQU 0x1C001481
SMC_BCR1_INIT	   EQU 0x10000000
SMC_BCR2_INIT	   EQU 0x10000C21

; External interface configuration register 
EBI_MUX_BASE       EQU 0xFFFE5000 
EBI_PIN_CONFIG     EQU 0x00005B3F 

; Reset, clocks and power control register (System clocks) 
RCPC_REG_BASE                EQU 0xFFFE2000
RCPC_CONTROL_OFFSET          EQU 0x00000000	; Control reg      
RCPC_REMAP_OFFSET            EQU 0x00000008   ; Remap memory reg 
RCPC_SYSCLK_PRESCALE_OFFSET  EQU 0x00000018   ; SysClk pre scale 
RCPC_SYSCLK_PRESCALE_DEFAULT EQU 0x00000001   ; 52Mhz            
RCPC_REMAP_INTERNAL_RAM      EQU 0x00000002

; TIMER registers used for blinking led 
TIMER0_REG_BASE              EQU 0xFFFC4000
TIMER0_CTRL_REG_OFFSET       EQU 0x00
TIMER0_CTRL_COUNT_CLEAR      EQU 0x01
TIMER0_STATUS_REG_OFFSET     EQU 0x0C
TIMER0_STATUS_CMP1           EQU 0x04
TIMER0_MATCH                 EQU 0xFFFF 
TIMER0_CMP_CAP_CTRL_INIT     EQU 0x4000
TIMER0_CTRL_INIT             EQU 0x1B

; GPIO  registers 
GPIO_REG_BASE                EQU 0xFFFDE000
GPIO_PDDR_OFFSET             EQU 0x00000004
GPIO_PDDDR_OFFSET            EQU 0x0000000C
GPIO_D1                      EQU 0x000000002

; Dip switch, Entry point for application, and valid switch 
; configurations  
DIP_SWITCH_ADRS  EQU 0x48200040
ANGEL_ENTRY      EQU EXTERNAL_SRAM_BASE
ANGEL_DEMO       EQU 0xFD
USER_DEMO        EQU 0xFE
SECTOR_SIZE      EQU 0x00010000
ANGEL_APP_SIZE   EQU (SECTOR_SIZE*1)
USER_APP_SIZE    EQU (SECTOR_SIZE*15)
ANGEL_APP_BASE   EQU (SECTOR_SIZE*1)
USER_APP_BASE    EQU (SECTOR_SIZE*2)
USER_ENTRY       EQU EXTERNAL_SRAM_BASE
	END