2410init.s

Embest EudKit-II教学系统配Samsung S3C2410处理器的部分测试程序。

#=======================================================================================================================
# File Name : 2410init.s
# Author	: embest
# Descript	: S3C2410x system start up codes
#			  Configure memory, ISR ,stacks
#			  Initialize C-variables
# History	:
#			(1) R.X.Huang, Programming modify, March 12, 2005
#=======================================================================================================================
	.include "option.inc"
	.include "memcfg.inc"
	.include "2410addr.inc"

/*------------------------------------------------------------------------------------------*/
/*	 								constant define						 				    */
/*------------------------------------------------------------------------------------------*/
.equ 	USERMODE,	0x10
.equ 	FIQMODE,	0x11
.equ 	IRQMODE,	0x12
.equ 	SVCMODE,	0x13
.equ 	ABORTMODE,	0x17
.equ 	UNDEFMODE,	0x1b
.equ 	MODEMASK,	0x1f
.equ 	NOINT,		0xc0
.equ    CPSR_IRQ_EN,	0x80		/*  */
.equ    CPSR_IRQ_MASK,	0x40		/* disable Interrupt Mode (IRQ) */
.equ    CPSR_FIQ_MASK,	0x80		/* disable Fast Interrupt Mode (FIQ) */

.macro HANDLER HandleLabel
    sub	    sp,sp,#4				/* decrement sp(to store jump address) */							
    stmfd   sp!,{r0}				/* PUSH the work register to stack(lr does't push because it return to original address) */
    ldr	    r0,=\HandleLabel		/* load the address of HandleXXX to r0 */
    ldr	    r0,[r0]					/* load the contents(service routine start address) of HandleXXX */
    str	    r0,[sp,#4]				/* store the contents(ISR) of HandleXXX to stack */
    ldmfd   sp!,{r0,pc}				/* POP the work register and pc(jump to ISR) */
.endm
    
	.extern			Image_RO_Base
	.extern			Image_RO_Limit	/* End of ROM code (=start of ROM data) */
	.extern			Image_RW_Base	/* Base of RAM to initialise */           
	.extern			Image_ZI_Base	/* Base and limit of area */              
	.extern			Image_ZI_Limit	/* to zero initialise */       
	.extern			Main			/* The main entry of mon program */

#=============================================================================================
# reset entry point  
#=============================================================================================
    .text
ENTRY:
# 1)The code, which converts to Big-endian, should be in little endian code.
# 2)The following little endian code will be compiled in Big-Endian mode. 
#   The code byte order should be changed as the memory bus width.
# 3)The pseudo instruction,.long can't be used here because the linker generates error.
.ifeq ENDIAN_CHANGE-1
.ifeq ENTRY_BUS_WIDTH-32
	b	ChangeBigEndian			@ .long 0xea000007 
.elseif ENTRY_BUS_WIDTH-16
	andeq	r14,r7,r0,lsl #20	@ .long 0x0007ea00
.elseif ENTRY_BUS_WIDTH-8
	streq	r0,[r0,-r10,ror #1]	@ .long 0x070000ea
.endif
.else
	b	ResetHandler 
.endif
	
	b	HandlerUndef		@ handler for Undefined mode
	b	HandlerSWI			@ handler for SWI interrupt
	b	HandlerPabort		@ handler for PAbort
	b	HandlerDabort		@ handler for DAbort
	b	.					@ reserved
	b	HandlerIRQ			@ handler for IRQ interrupt 
	b	HandlerFIQ			@ handler for FIQ interrupt
#- 0x20
	b	EnterPWDN

#=============================================================================================
# ChangeBigEndian 
# Should be stored in memory address at 0x24 
#=============================================================================================
ChangeBigEndian:
#- 0x24
.ifeq ENTRY_BUS_WIDTH-32
	.long	0xee110f10	@ 0xee110f10 => mrc p15,0,r0,c1,c0,0
	.long	0xe3800080	@ 0xe3800080 => orr r0,r0,#0x80#  //Big-endian
	.long	0xee010f10	@ 0xee010f10 => mcr p15,0,r0,c1,c0,0
.endif
.ifeq ENTRY_BUS_WIDTH-16
	.long 0x0f10ee11
	.long 0x0080e380	
	.long 0x0f10ee01	
.endif
.ifeq ENTRY_BUS_WIDTH-8
	.long 0x100f11ee	
	.long 0x800080e3	
	.long 0x100f01ee	
.endif
	.long 0xffffffff		@ swinv 0xffffff is similar with NOP and run well in both endian mode. 
	.long 0xffffffff
	.long 0xffffffff
	.long 0xffffffff
	.long 0xffffffff
	b ResetHandler
	
#=============================================================================================
# EnterPWDN  
# Function for entering power down mode
# 1. SDRAM should be in self-refresh mode.
# 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.
# 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.
# 4. The I-cache may have to be turned on. 
# 5. The location of the following code may have not to be changed.
#=============================================================================================
# void EnterPWDN(int CLKCON); 
EnterPWDN:			
	mov r2,r0			@ r2=rCLKCON
	tst r0,#0x8			@ POWER_OFF mode?
	bne ENTER_POWER_OFF

ENTER_STOP:	
	ldr r0,=REFRESH		
	ldr r3,[r0]			@ r3=rREFRESH	
	mov r1, r3
	orr r1, r1, #BIT_SELFREFRESH
	str r1, [r0]		@ Enable SDRAM self-refresh
	mov r1,#16			@ wait until self-refresh is issued. may not be needed.
B0:
	subs r1,r1,#1
	bne B0
	ldr r0,=CLKCON		@ enter STOP mode.
	str r2,[r0] 
	mov r1,#32
F0:	
	subs r1,r1,#1		@ 1) wait until the STOP mode is in effect.
	bne B0				@ 2) Or wait here until the CPU&Peripherals will be turned-off
	
# Entering POWER_OFF mode, only the reset by wake-up is available.
	ldr r0,=REFRESH		@ exit from SDRAM self refresh mode.
	str r3,[r0]	
	MOV_PC_LR

#=============================================================================================
# ENTER_POWER_OFF  
#=============================================================================================
ENTER_POWER_OFF:	
# NOTE.
# 1) rGSTATUS3 should have the return address after wake-up from POWER_OFF mode.	
	ldr r0,=REFRESH		
	ldr r1,[r0]			@ r1=rREFRESH	
	orr r1, r1, #BIT_SELFREFRESH
	str r1, [r0]		@ Enable SDRAM self-refresh
	
	mov r1,#16	   		@ Wait until self-refresh is issued,which may not be needed.
B1:	subs r1,r1,#1
	bne B1
	ldr r1,=MISCCR
	ldr	r0,[r1]
	orr	r0,r0,#(7<<17)  @ Make sure that SCLK0:SCLK->0, SCLK1:SCLK->0, SCKE=L during boot-up 
	str	r0,[r1]
	ldr r0,=CLKCON
	str r2,[r0]
	b .					@ CPU will die here.
	
#=============================================================================================
# WAKEUP_POWER_OFF  
#=============================================================================================
WAKEUP_POWER_OFF:
# Release SCLKn after wake-up from the POWER_OFF mode.
	ldr r1,=MISCCR
	ldr	r0,[r1]
	bic	r0,r0,#(7<<17)  @ SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H
	str	r0,[r1]
	
# Set memory control registers
    ldr	r0,=SMRDATA
	ldr	r1,=BWSCON		@ BWSCON Address
	add	r2, r0, #52		@ End address of SMRDATA
B2:       
	ldr	r3, [r0], #4    
	str	r3, [r1], #4    
	cmp	r2, r0		
	bne	B2
	mov r1,#256
B3:	
	subs r1,r1,#1		@ 1) wait until the SelfRefresh is released.
	bne B3	

	ldr r1,=GSTATUS3 	@ GSTATUS3 has the start address just after POWER_OFF wake-up
	ldr r0,[r1]
	mov pc,r0

#=============================================================================================
# ARM core's exception entry  
#=============================================================================================
	.align   
HandlerFIQ:      HANDLER HandleFIQ
HandlerIRQ:      HANDLER HandleIRQ
HandlerUndef:    HANDLER HandleUndef
HandlerSWI:      HANDLER HandleSWI
HandlerDabort:   HANDLER HandleDabort
HandlerPabort:   HANDLER HandlePabort

IsrIRQ:  
	sub	sp,sp,#4       @ reserved for PC
	stmfd	sp!,{r8-r9}   
	
	ldr	r9,=INTOFFSET
	ldr	r9,[r9]
	ldr	r8,=HandleEINT0
	add	r8,r8,r9,lsl #2
	ldr	r8,[r8]
	str	r8,[sp,#8]
	ldmfd	sp!,{r8-r9,pc}

#=============================================================================================
# ResetHandler  
#=============================================================================================
ResetHandler:
	ldr	r0,=WTCON       @ watch dog disable 
	ldr	r1,=0x0