📄 at91sam7s64.inc
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# *** Register offset in AT91S_PMC structure ***
.equ PMC_SCER , ( 0) /* System Clock Enable Register */
.equ PMC_SCDR , ( 4) /* System Clock Disable Register */
.equ PMC_SCSR , ( 8) /* System Clock Status Register */
.equ PMC_PCER , (16) /* Peripheral Clock Enable Register */
.equ PMC_PCDR , (20) /* Peripheral Clock Disable Register */
.equ PMC_PCSR , (24) /* Peripheral Clock Status Register */
.equ PMC_MOR , (32) /* Main Oscillator Register */
.equ PMC_MCFR , (36) /* Main Clock Frequency Register */
.equ PMC_PLLR , (44) /* PLL Register */
.equ PMC_MCKR , (48) /* Master Clock Register */
.equ PMC_PCKR , (64) /* Programmable Clock Register */
.equ PMC_IER , (96) /* Interrupt Enable Register */
.equ PMC_IDR , (100) /* Interrupt Disable Register */
.equ PMC_SR , (104) /* Status Register */
.equ PMC_IMR , (108) /* Interrupt Mask Register */
# -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
.equ AT91C_PMC_PCK , (0x1 << 0) /* (PMC) Processor Clock */
.equ AT91C_PMC_UDP , (0x1 << 7) /* (PMC) USB Device Port Clock */
.equ AT91C_PMC_PCK0 , (0x1 << 8) /* (PMC) Programmable Clock Output */
.equ AT91C_PMC_PCK1 , (0x1 << 9) /* (PMC) Programmable Clock Output */
.equ AT91C_PMC_PCK2 , (0x1 << 10) /* (PMC) Programmable Clock Output */
.equ AT91C_PMC_PCK3 , (0x1 << 11) /* (PMC) Programmable Clock Output */
# -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
# -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
# -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
# -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
# -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
# -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
.equ AT91C_PMC_CSS ,(0x3 << 0) /* (PMC) Programmable Clock Selection */
.equ AT91C_PMC_CSS_SLOW_CLK , (0x0) /* (PMC) Slow Clock is selected */
.equ AT91C_PMC_CSS_MAIN_CLK , (0x1) /* (PMC) Main Clock is selected */
.equ AT91C_PMC_CSS_PLL_CLK , (0x3) /* (PMC) Clock from PLL is selected */
.equ AT91C_PMC_PRES , (0x7 << 2) /* (PMC) Programmable Clock Prescaler */
.equ AT91C_PMC_PRES_CLK , (0x0 << 2) /* (PMC) Selected clock */
.equ AT91C_PMC_PRES_CLK_2 , (0x1 << 2) /* (PMC) Selected clock divided by 2 */
.equ AT91C_PMC_PRES_CLK_4 , (0x2 << 2) /* (PMC) Selected clock divided by 4 */
.equ AT91C_PMC_PRES_CLK_8 , (0x3 << 2) /* (PMC) Selected clock divided by 8 */
.equ AT91C_PMC_PRES_CLK_16 , (0x4 << 2) /* (PMC) Selected clock divided by 16 */
.equ AT91C_PMC_PRES_CLK_32 , (0x5 << 2) /* (PMC) Selected clock divided by 32 */
.equ AT91C_PMC_PRES_CLK_64 , (0x6 << 2) /* (PMC) Selected clock divided by 64 */
# -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
# -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
.equ AT91C_PMC_MOSCS , (0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */
.equ AT91C_PMC_LOCK , (0x1 << 2) /* (PMC) PLL Status/Enable/Disable/Mask */
.equ AT91C_PMC_MCKRDY , (0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
.equ AT91C_PMC_PCK0RDY , (0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
.equ AT91C_PMC_PCK1RDY , (0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
.equ AT91C_PMC_PCK2RDY , (0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
.equ AT91C_PMC_PCK3RDY , (0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
# -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
# -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
# -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Reset Controller Interface
# *****************************************************************************
# *** Register offset in AT91S_RSTC structure ***
.equ RSTC_RCR , ( 0) /* Reset Control Register
.equ RSTC_RSR , ( 4) /* Reset Status Register */
.equ RSTC_RMR , ( 8) /* Reset Mode Register */
# -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
.equ AT91C_SYSC_PROCRST , (0x1 << 0) /* (RSTC) Processor Reset */
.equ AT91C_SYSC_ICERST , (0x1 << 1) /* (RSTC) ICE Interface Reset */
.equ AT91C_SYSC_PERRST , (0x1 << 2) /* (RSTC) Peripheral Reset */
.equ AT91C_SYSC_EXTRST , (0x1 << 3) /* (RSTC) External Reset */
.equ AT91C_SYSC_KEY , (0xFF << 24) /* (RSTC) Password */
# -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
.equ AT91C_SYSC_URSTS , (0x1 << 0) /* (RSTC) User Reset Status */
.equ AT91C_SYSC_RSTTYP , (0x7 << 8) /* (RSTC) Reset Type */
.equ AT91C_SYSC_RSTTYP_GENERAL , (0x1 << 8) /* (RSTC) General reset. Both VDDCORE and VDDBU rising. */
.equ AT91C_SYSC_RSTTYP_WAKEUP , (0x2 << 8) /* (RSTC) WakeUp Reset. VDDCORE rising. */
.equ AT91C_SYSC_RSTTYP_WATCHDOG , (0x3 << 8) /* (RSTC) Watchdog Reset. Watchdog overflow occured. */
.equ AT91C_SYSC_RSTTYP_SOFTWARE , (0x4 << 8) /* (RSTC) Software Reset. Processor reset required by the software. */
.equ AT91C_SYSC_RSTTYP_USER , (0x5 << 8) /* (RSTC) User Reset. NRST pin detected low. */
.equ AT91C_SYSC_NRSTL , (0x1 << 16) /* (RSTC) NRST pin level */
.equ AT91C_SYSC_SRCMP , (0x1 << 17) /* (RSTC) Software Reset Command in Progress. */
# -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
.equ AT91C_SYSC_URSTEN , (0x1 << 0) /* (RSTC) User Reset Enable */
.equ AT91C_SYSC_URSTIEN , (0x1 << 4) /* (RSTC) User Reset Interrupt Enable */
.equ AT91C_SYSC_ERSTL , (0xF << 8) /* (RSTC) User Reset Enable */
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