📄 at91sam7s64.inc
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.equ PDC_TPR , ( 8) /* Transmit Pointer Register */
.equ PDC_TCR , (12) /* Transmit Counter Register */
.equ PDC_RNPR , (16) /* Receive Next Pointer Register */
.equ PDC_RNCR , (20) /* Receive Next Counter Register */
.equ PDC_TNPR , (24) /* Transmit Next Pointer Register */
.equ PDC_TNCR , (28) /* Transmit Next Counter Register */
.equ PDC_PTCR , (32) /* PDC Transfer Control Register */
.equ PDC_PTSR , (36) /* PDC Transfer Status Register */
# -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
.equ AT91C_PDC_RXTEN , (0x1 << 0) /* (PDC) Receiver Transfer Enable */
.equ AT91C_PDC_RXTDIS , (0x1 << 1) /* (PDC) Receiver Transfer Disable */
.equ AT91C_PDC_TXTEN , (0x1 << 8) /* (PDC) Transmitter Transfer Enable */
.equ AT91C_PDC_TXTDIS , (0x1 << 9) /* (PDC) Transmitter Transfer Disable */
# -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Parallel Input Output Controler
# *****************************************************************************
# *** Register offset in AT91S_PIO structure ***
.equ PIO_PER , ( 0) /* PIO Enable Register */
.equ PIO_PDR , ( 4) /* PIO Disable Register */
.equ PIO_PSR , ( 8) /* PIO Status Register */
.equ PIO_OER , (16) /* Output Enable Register */
.equ PIO_ODR , (20) /* Output Disable Registerr */
.equ PIO_OSR , (24) /* Output Status Register */
.equ PIO_IFER , (32) /* Input Filter Enable Register */
.equ PIO_IFDR , (36) /* Input Filter Disable Register */
.equ PIO_IFSR , (40) /* Input Filter Status Register */
.equ PIO_SODR , (48) /* Set Output Data Register */
.equ PIO_CODR , (52) /* Clear Output Data Register */
.equ PIO_ODSR , (56) /* Output Data Status Register */
.equ PIO_PDSR , (60) /* Pin Data Status Register */
.equ PIO_IER , (64) /* Interrupt Enable Register */
.equ PIO_IDR , (68) /* Interrupt Disable Register */
.equ PIO_IMR , (72) /* Interrupt Mask Register */
.equ PIO_ISR , (76) /* Interrupt Status Register */
.equ PIO_MDER , (80) /* Multi-driver Enable Register */
.equ PIO_MDDR , (84) /* Multi-driver Disable Register */
.equ PIO_MDSR , (88) /* Multi-driver Status Register */
.equ PIO_PPUDR , (96) /* Pull-up Disable Register */
.equ PIO_PPUER , (100) /* Pull-up Enable Register */
.equ PIO_PPUSR , (104) /* Pad Pull-up Status Register */
.equ PIO_ASR , (112) /* Select A Register */
.equ PIO_BSR , (116) /* Select B Register */
.equ PIO_ABSR , (120) /* AB Select Status Register */
.equ PIO_OWER , (160) /* Output Write Enable Register */
.equ PIO_OWDR , (164) /* Output Write Disable Register */
.equ PIO_OWSR , (168) /* Output Write Status Register */
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Clock Generator Controler
# *****************************************************************************
# *** Register offset in AT91S_CKGR structure ***
.equ CKGR_MOR , ( 0) /* Main Oscillator Register
.equ CKGR_MCFR , ( 4) /* Main Clock Frequency Register
.equ CKGR_PLLR (12) /* PLL Register
# -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
.equ AT91C_CKGR_MOSCEN , (0x1 << 0) /* (CKGR) Main Oscillator Enable */
.equ AT91C_CKGR_OSCBYPASS , (0x1 << 1) /* (CKGR) Main Oscillator Bypass */
.equ AT91C_CKGR_OSCOUNT , (0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */
# -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
.equ AT91C_CKGR_MAINF , (0xFFFF << 0) /* (CKGR) Main Clock Frequency */
.equ AT91C_CKGR_MAINRDY , (0x1 << 16) /* (CKGR) Main Clock Ready */
# -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
.equ AT91C_CKGR_DIV , (0xFF << 0) /* (CKGR) Divider Selected */
.equ AT91C_CKGR_DIV_0 , (0x0) /* (CKGR) Divider output is 0 */
.equ AT91C_CKGR_DIV_BYPASS , (0x1) /* (CKGR) Divider is bypassed */
.equ AT91C_CKGR_PLLCOUNT , (0x3F << 8) /* (CKGR) PLL Counter */
.equ AT91C_CKGR_OUT , (0x3 << 14) /* (CKGR) PLL Output Frequency Range */
.equ AT91C_CKGR_OUT_0 , (0x0 << 14) /* (CKGR) Please refer to the PLL datasheet */
.equ AT91C_CKGR_OUT_1 , (0x1 << 14) /* (CKGR) Please refer to the PLL datasheet */
.equ AT91C_CKGR_OUT_2 , (0x2 << 14) /* (CKGR) Please refer to the PLL datasheet */
.equ AT91C_CKGR_OUT_3 , (0x3 << 14) /* (CKGR) Please refer to the PLL datasheet */
.equ AT91C_CKGR_MUL , (0x7FF << 16)/* (CKGR) PLL Multiplier */
.equ AT91C_CKGR_USBDIV , (0x3 << 28)/* (CKGR) Divider for USB Clocks */
.equ AT91C_CKGR_USBDIV_0 , (0x0 << 28)/* (CKGR) Divider output is PLL clock output */
.equ AT91C_CKGR_USBDIV_1 , (0x1 << 28)/* (CKGR) Divider output is PLL clock output divided by 2 */
.equ AT91C_CKGR_USBDIV_2 , (0x2 << 28)/* (CKGR) Divider output is PLL clock output divided by 4 */
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Power Management Controler
# *****************************************************************************
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